diff options
| author | Graziano Misuraca <gmisuraca@nvidia.com> | 2012-05-18 16:32:34 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-07-12 10:12:08 +0530 |
| commit | 3dbd2d8c7ce9d20d6c569ee1dcf7c3bdcf1a01f4 (patch) | |
| tree | d8e6256079a41aac8f9d2aefaf864be0c0f3fe0a /arch/arm/mach-tegra/tegra3_dvfs.c | |
| parent | 7f9cd401e115ba71076e0b58a9f7eeb791da1391 (diff) | |
ARM: Tegra: Enable 900MHz at 1V on restricted pll_m
Allow pll_m to reach 900MHz at 1V on T30, T33, T37
rev A02+ SKUs.
Bug 891320
Change-Id: Idbfb10014ae2a1d06abc3bc1d0bed59c583fac98
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/103453
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 81be6c2ffcc1..72bfb231eef2 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -293,7 +293,7 @@ static struct dvfs core_dvfs_table[] = { */ CORE_DVFS("pll_m", -1, 1, KHZ, 533000, 667000, 667000, 800000, 800000, 1066000, 1066000, 1066000, 1066000), #ifdef CONFIG_TEGRA_PLLM_RESTRICTED - CORE_DVFS("pll_m", 2, 1, KHZ, 533000, 800000, 800000, 800000, 800000, 1066000, 1066000, 1066000, 1066000), + CORE_DVFS("pll_m", 2, 1, KHZ, 533000, 900000, 900000, 900000, 900000, 1066000, 1066000, 1066000, 1066000), #endif /* Core voltages (mV): 950, 1000, 1050, 1100, 1150, 1200, 1250, 1300, 1350 */ /* Clock limits for I/O peripherals */ |