diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2012-05-03 22:33:03 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:09:07 -0700 |
| commit | 350015f9b9a44811e38ca692478104f85c744223 (patch) | |
| tree | bf0f29ed73cf67a906732a4982290586516b9618 /arch/arm/mach-tegra/tegra3_emc.c | |
| parent | 04649f90ebe5a10dae979a2370e478fd6038b4fc (diff) | |
fixup: emc: move clk_min to pdev
Rebase-Id: R83b293e052f09fce49cd499e555d1347d72687d4
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 4fdda2068f53..7a3a824d8ff1 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -1008,6 +1008,20 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENOMEM; } + emc = clk_get(&pdev->dev, NULL); + if (IS_ERR(emc)) { + dev_err(&pdev->dev, "failed to get clock\n"); + return -EINVAL; + } + + dram_type = (emc_readl(EMC_FBIO_CFG5) & + EMC_CFG5_TYPE_MASK) >> EMC_CFG5_TYPE_SHIFT; + if (dram_type == DRAM_TYPE_DDR3) + emc->min_rate = EMC_MIN_RATE_DDR3; + + dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */ + emc_cfg_saved = emc_readl(EMC_CFG); + pdev->dev.platform_data = pdata; if (!pdata->tables || !pdata->num_tables) { @@ -1126,19 +1140,6 @@ void tegra_init_dram_bit_map(const u32 *bit_map, int map_size) dram_to_soc_bit_map = bit_map; } -void tegra_emc_dram_type_init(struct clk *c) -{ - emc = c; - - dram_type = (emc_readl(EMC_FBIO_CFG5) & - EMC_CFG5_TYPE_MASK) >> EMC_CFG5_TYPE_SHIFT; - if (dram_type == DRAM_TYPE_DDR3) - emc->min_rate = EMC_MIN_RATE_DDR3; - - dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */ - emc_cfg_saved = emc_readl(EMC_CFG); -} - int tegra_emc_get_dram_type(void) { return dram_type; |