diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-07-11 22:55:04 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:38 -0800 |
| commit | 3faad7cb45890ddeb6eeb3623fb289bfe583de42 (patch) | |
| tree | 1c622e036edb3dd71a5d058d4fd945441fd81eb4 /arch/arm/mach-tegra/tegra3_emc.h | |
| parent | 18163a0a7e1f99be1adaa97ff87b667c1247d397 (diff) | |
ARM: tegra: clock: Support Tegra3 EMC DFS table revision
Support Tegra3 EMC DFS table revision 3.1 that includes two additional
EMC shadow registers (reserved with previous table revision 3.0).
Bug 836260
Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb
Reviewed-on: http://git-master/r/40749
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.h')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h index ee91b4d596fe..2e715498abec 100644 --- a/arch/arm/mach-tegra/tegra3_emc.h +++ b/arch/arm/mach-tegra/tegra3_emc.h @@ -22,7 +22,7 @@ #ifndef _MACH_TEGRA_TEGRA3_EMC_H #define _MACH_TEGRA_TEGRA3_EMC_H -#define TEGRA_EMC_NUM_REGS 105 +#define TEGRA_EMC_NUM_REGS 110 #define TEGRA_EMC_BRIDGE_RATE_MIN 300000000 #define TEGRA_EMC_BRIDGE_MVOLTS_MIN 1200 @@ -134,6 +134,7 @@ enum { #define EMC_MRR 0xec #define EMC_XM2DQSPADCTRL3 0xf8 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE (0x1 << 5) +#define EMC_FBIO_SPARE 0x100 #define EMC_FBIO_CFG5 0x104 #define EMC_CFG5_TYPE_SHIFT 0x0 @@ -153,6 +154,7 @@ enum { }; #define EMC_FBIO_CFG6 0x114 +#define EMC_CFG_RSV 0x120 #define EMC_AUTO_CAL_CONFIG 0x2a4 #define EMC_AUTO_CAL_INTERVAL 0x2a8 #define EMC_AUTO_CAL_STATUS 0x2ac |