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authorVinod G <vinodg@nvidia.com>2011-04-13 14:33:49 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-04-26 15:55:51 -0700
commiteee725de1119955fa792c8542b63a0d619745744 (patch)
tree579dc1656eb2a8aa69ce4070c89981b24e49917d /arch/arm/mach-tegra/tegra3_i2s.c
parent409af048b6e333588b022338cce6acdeb7c25f68 (diff)
arm: tegra: suspend/resume calls to audioswitch
added suspend/resume calls to audioswitch and i2s code is using those calls. Original-Change-Id: I475f43b67feeab61f1a3fd84f446ba5c4e126f87 Reviewed-on: http://git-master/r/27697 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Tested-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Change-Id: Ie01d6d20c24902a42461bcdb42d9bef57c7cc63b
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_i2s.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_i2s.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_i2s.c b/arch/arm/mach-tegra/tegra3_i2s.c
index ad8f22565587..807164782303 100644
--- a/arch/arm/mach-tegra/tegra3_i2s.c
+++ b/arch/arm/mach-tegra/tegra3_i2s.c
@@ -150,10 +150,12 @@ void i2s_suspend(int ifc)
{
i2s_save_registers(ifc);
i2s_clock_disable(ifc);
+ audio_switch_suspend();
}
void i2s_resume(int ifc)
{
+ audio_switch_resume();
i2s_clock_enable(ifc);
i2s_restore_registers(ifc);
}
@@ -862,6 +864,10 @@ int i2s_clock_enable(int ifc)
int err = 0;
struct i2s_controller_info *info = &i2s_cont_info[ifc];
+ err = audio_switch_enable_clock();
+ if (err)
+ return err;
+
if (info->i2sprop.i2s_clk && (info->i2sprop.master_mode == true)) {
clk_set_rate(info->i2sprop.i2s_clk, info->i2sprop.clk_rate);
@@ -878,7 +884,7 @@ int i2s_clock_enable(int ifc)
info->clk_refs++;
}
- I2S_DEBUG_PRINT(" enable clock count 0x%x \n", info->clk_refs);
+ I2S_DEBUG_PRINT(" i2s enable clock count 0x%x \n", info->clk_refs);
return err;
}
@@ -919,7 +925,8 @@ int i2s_clock_disable(int ifc)
}
}
- I2S_DEBUG_PRINT(" disable clock count 0x%x \n", info->clk_refs);
+ audio_switch_disable_clock();
+ I2S_DEBUG_PRINT(" i2s disable clock count 0x%x \n", info->clk_refs);
return 0;
}