ARM: tegra: dvfs: Build DFLL voltage selection map

Added an option to build DFLL voltage selection map dynamically, if
static map is not provided in platform data. Two building algorithms:

- Use regulator interface to match regulator selector to voltage level,
and linear conversion of selector to register values. Applied when vdd
supply with I2C interface and internal voltage selection register is
connected.

- Directly map PWM duty cycle to voltage level linearly, and record number
of high PWM steps as register setting. Applied when vdd supply driven by
DFLL PWM data output is connected.

Conversion coefficients are added to DFLL platform data, and in both
cases above can be specified instead of static voltage map.

Change-Id: I1c41e7d13df564affb5cb02441d57a90128c14a4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/356954
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.h b/arch/arm/mach-tegra/tegra_cl_dvfs.h
index ecca61e8f8aa..59fdb37f8696 100644
--- a/arch/arm/mach-tegra/tegra_cl_dvfs.h
+++ b/arch/arm/mach-tegra/tegra_cl_dvfs.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra_cl_dvfs.h
  *
- * Copyright (C) 2012 NVIDIA Corporation.
+ * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -80,10 +80,14 @@ struct tegra_cl_dvfs_platform_data {
 			u8			reg;
 			u16			slave_addr;
 			bool			addr_10;
+			u32			sel_mul;
+			u32			sel_offs;
 		} pmu_i2c;
 		struct {
 			unsigned long		pwm_rate;
 			bool			delta_mode;
+			int			min_uV;
+			int			step_uV;
 
 			enum tegra_cl_dvfs_pwm_bus pwm_bus;
 			int			pwm_pingroup;