diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-08-09 22:09:29 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:31:34 -0700 |
| commit | 0d328a216f284f18dafc43e061241425a13f478e (patch) | |
| tree | 4d03e3787c0abd41cb7a3cc66cc1714f1f2044a2 /arch/arm/mach-tegra/tegra_cl_dvfs.h | |
| parent | 28c3c4bb3668e85bdfd84f268e56b178e847b369 (diff) | |
ARM: tegra11: dvfs: Rename CL-DVFS data structure
Changed name of the structure with dfll tuning parameters in CL-DVFS
object from "soc_data" to more appropriate "dfll_data". Updated
member names to remove redundant (now) dfll_ prefix (one exception -
kept dfll_clk_name member for consistency with other dfll clock
references).
Change-Id: I08e83ea7981b32ebd776a9eb2a94cf2b972a0085
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/122818
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Rebase-Id: R6b3b90d650c59cb0ff0ac646d5567b4becb6acd9
Diffstat (limited to 'arch/arm/mach-tegra/tegra_cl_dvfs.h')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.h b/arch/arm/mach-tegra/tegra_cl_dvfs.h index 3f3a23d9abfc..54f09f87c498 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.h +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.h @@ -84,13 +84,13 @@ struct tegra_cl_dvfs_platform_data { struct tegra_cl_dvfs_cfg_param *cfg_param; }; -struct tegra_cl_dvfs_soc_data { +struct tegra_cl_dvfs_dfll_data { const char *dfll_clk_name; u32 tune0; u32 tune1; - unsigned long dfll_droop_rate_min; - unsigned long dfll_out_rate_min; - int dfll_millivolts_min; + unsigned long droop_rate_min; + unsigned long out_rate_min; + int millivolts_min; }; struct dfll_rate_req { @@ -101,7 +101,7 @@ struct dfll_rate_req { struct tegra_cl_dvfs { u32 cl_base; - struct tegra_cl_dvfs_soc_data *soc_data; + struct tegra_cl_dvfs_dfll_data *dfll_data; struct tegra_cl_dvfs_platform_data *p_data; struct dvfs *safe_dvfs; @@ -128,7 +128,7 @@ struct tegra_cl_dvfs { #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS void tegra_cl_dvfs_set_plarform_data(struct tegra_cl_dvfs_platform_data *data); -void tegra_cl_dvfs_set_soc_data(struct tegra_cl_dvfs_soc_data *data); +void tegra_cl_dvfs_set_dfll_data(struct tegra_cl_dvfs_dfll_data *data); int tegra_init_cl_dvfs(struct tegra_cl_dvfs *cld); void tegra_cl_dvfs_disable(struct tegra_cl_dvfs *cld); @@ -141,8 +141,8 @@ unsigned long tegra_cl_dvfs_request_get(struct tegra_cl_dvfs *cld); static inline void tegra_cl_dvfs_set_plarform_data( struct tegra_cl_dvfs_platform_data *data) {} -static inline void tegra_cl_dvfs_set_soc_data( - struct tegra_cl_dvfs_soc_data *data) +static inline void tegra_cl_dvfs_set_dfll_data( + struct tegra_cl_dvfs_dfll_data *data) {} static inline int tegra_init_cl_dvfs(struct tegra_cl_dvfs *cld) { return -ENOSYS; } |