ARM: tegra: Move common timer code into timer.c

The system timer initialization code for Tegra2 and Tegra3 is
essentially the same except for the actual physical timer used and the
range of possible reference clock frequencies. This change removes the
needless duplication of code and restructures the system timer code into
common and SOC-specific parts.

Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15

1 files changed, 5 insertions, 211 deletions

diff --git a/arch/arm/mach-tegra/timer-t2.c b/arch/arm/mach-tegra/timer-t2.c
index 0ee51b6047ab..d433133474bc 100644
--- a/arch/arm/mach-tegra/timer-t2.c
+++ b/arch/arm/mach-tegra/timer-t2.c
@@ -38,203 +38,24 @@
 
 #include "board.h"
 #include "clock.h"
-
-#define RTC_SECONDS            0x08
-#define RTC_SHADOW_SECONDS     0x0c
-#define RTC_MILLISECONDS       0x10
-
-#define TIMERUS_CNTR_1US 0x10
-#define TIMERUS_USEC_CFG 0x14
-#define TIMERUS_CNTR_FREEZE 0x4c
+#include "timer.h"
 
 #define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE)
 #define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE)
 #define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE)
 #define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE)
 
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-
-static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
-static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
-
-static struct timespec persistent_ts;
-static u64 persistent_ms, last_persistent_ms;
-static u32 usec_offset;
-static bool usec_suspended;
-
 #define timer_writel(value, reg) \
 	__raw_writel(value, (u32)timer_reg_base + (reg))
 #define timer_readl(reg) \
 	__raw_readl((u32)timer_reg_base + (reg))
 
-static int tegra_timer_set_next_event(unsigned long cycles,
-					 struct clock_event_device *evt)
-{
-	u32 reg;
-
-	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-	timer_writel(reg, TIMER3_OFFSET + TIMER_PTV);
-
-	return 0;
-}
-
-static void tegra_timer_set_mode(enum clock_event_mode mode,
-				    struct clock_event_device *evt)
-{
-	u32 reg;
-
-	timer_writel(0, TIMER3_OFFSET + TIMER_PTV);
-
-	switch (mode) {
-	case CLOCK_EVT_MODE_PERIODIC:
-		reg = 0xC0000000 | ((1000000/HZ)-1);
-		timer_writel(reg, TIMER3_OFFSET + TIMER_PTV);
-		break;
-	case CLOCK_EVT_MODE_ONESHOT:
-		break;
-	case CLOCK_EVT_MODE_UNUSED:
-	case CLOCK_EVT_MODE_SHUTDOWN:
-	case CLOCK_EVT_MODE_RESUME:
-		break;
-	}
-}
-
-static struct clock_event_device tegra_clockevent = {
-	.name		= "timer0",
-	.rating		= 300,
-	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-	.set_next_event	= tegra_timer_set_next_event,
-	.set_mode	= tegra_timer_set_mode,
-};
-
-static DEFINE_CLOCK_DATA(cd);
-
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
- * This gives a resolution of about 1us and a wrap period of about 1h11min.
- */
-#define SC_MULT		4194304000u
-#define SC_SHIFT	22
-
-static u32 notrace tegra_read_usec(void)
-{
-	u32 cyc = usec_offset;
-	if (!usec_suspended)
-		cyc += timer_readl(TIMERUS_CNTR_1US);
-	return cyc;
-}
-
-unsigned long long notrace sched_clock(void)
-{
-	u32 cyc = tegra_read_usec();
-	return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
-}
 
-static void notrace tegra_update_sched_clock(void)
-{
-	u32 cyc = tegra_read_usec();
-	update_sched_clock(&cd, cyc, (u32)~0);
-}
-
-/*
- * tegra_rtc_read - Reads the Tegra RTC registers
- * Care must be taken that this funciton is not called while the
- * tegra_rtc driver could be executing to avoid race conditions
- * on the RTC shadow register
- */
-u64 tegra_rtc_read_ms(void)
-{
-	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
-	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
-	return (u64)s * MSEC_PER_SEC + ms;
-}
-
-/*
- * read_persistent_clock -  Return time from a persistent clock.
- *
- * Reads the time from a source which isn't disabled during PM, the
- * 32k sync timer.  Convert the cycles elapsed since last read into
- * nsecs and adds to a monotonically increasing timespec.
- * Care must be taken that this funciton is not called while the
- * tegra_rtc driver could be executing to avoid race conditions
- * on the RTC shadow register
- */
-void read_persistent_clock(struct timespec *ts)
-{
-	u64 delta;
-	struct timespec *tsp = &persistent_ts;
-
-	last_persistent_ms = persistent_ms;
-	persistent_ms = tegra_rtc_read_ms();
-	delta = persistent_ms - last_persistent_ms;
-
-	timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
-	*ts = *tsp;
-}
-
-static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
-{
-	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-	timer_writel(1<<30, TIMER3_OFFSET + TIMER_PCR);
-	evt->event_handler(evt);
-	return IRQ_HANDLED;
-}
-
-static struct irqaction tegra_timer_irq = {
-	.name		= "timer0",
-	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
-	.handler	= tegra_timer_interrupt,
-	.dev_id		= &tegra_clockevent,
-	.irq		= INT_TMR3,
-};
-
-static u32 usec_config;
-
-static int tegra_timer_suspend(void)
-{
-	usec_config = timer_readl(TIMERUS_USEC_CFG);
-
-	usec_offset += timer_readl(TIMERUS_CNTR_1US);
-	usec_suspended = true;
-
-	return 0;
-}
-
-static void tegra_timer_resume(void)
-{
-	timer_writel(usec_config, TIMERUS_USEC_CFG);
-
-	usec_offset -= timer_readl(TIMERUS_CNTR_1US);
-	usec_suspended = false;
-}
-
-static struct syscore_ops tegra_timer_syscore_ops = {
-	.suspend = tegra_timer_suspend,
-	.resume = tegra_timer_resume,
-};
+static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
 
-static void __init tegra_init_timer(void)
+void __init tegra2_init_timer(u32 *offset, int *irq)
 {
-	struct clk *clk;
 	unsigned long rate = clk_measure_input_freq();
-	int ret;
-
-	clk = clk_get_sys("timer", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_enable(clk);
-
-	/*
-	 * rtc registers are used by read_persistent_clock, keep the rtc clock
-	 * enabled
-	 */
-	clk = clk_get_sys("rtc-tegra", NULL);
-	BUG_ON(IS_ERR(clk));
-	clk_enable(clk);
-
-#ifdef CONFIG_HAVE_ARM_TWD
-	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
-#endif
 
 	switch (rate) {
 	case 12000000:
@@ -253,37 +74,10 @@ static void __init tegra_init_timer(void)
 		WARN(1, "Unknown clock rate");
 	}
 
-	init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
-			       1000000, SC_MULT, SC_SHIFT);
-
-	if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-		"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
-		printk(KERN_ERR "Failed to register clocksource\n");
-		BUG();
-	}
-
-	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-	if (ret) {
-		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
-		BUG();
-	}
-
-	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
-	tegra_clockevent.max_delta_ns =
-		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
-	tegra_clockevent.min_delta_ns =
-		clockevent_delta2ns(0x1, &tegra_clockevent);
-	tegra_clockevent.cpumask = cpu_all_mask;
-	tegra_clockevent.irq = tegra_timer_irq.irq;
-	clockevents_register_device(&tegra_clockevent);
-
-	register_syscore_ops(&tegra_timer_syscore_ops);
+	*offset = TIMER3_OFFSET;
+	*irq = INT_TMR3;
 }
 
-struct sys_timer tegra_timer = {
-	.init = tegra_init_timer,
-};
-
 void tegra2_lp2_set_trigger(unsigned long cycles)
 {
 	timer_writel(0, TIMER4_OFFSET + TIMER_PTV);