diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-04-11 17:10:54 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:31 -0800 |
| commit | d0cbbc7182b02a465f13c4d9c0e9da23b389720c (patch) | |
| tree | 45fa0a0512ad665460c0e493d1ac75892ce50b6f /arch/arm/mach-tegra/timer-t2.c | |
| parent | f1768e3186b25fa2ff57752db7ad3c13a94d35e9 (diff) | |
ARM: tegra: timer: Clean up Tegra2 timer code
Remove extraneous code.
Clean up timer register addresses.
Original-Change-Id: I459e5b1aa7062d8454b5c064354fe71ef3a737d4
Reviewed-on: http://git-master/r/27444
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I353886d350bb8389aa12dc2da03b3a3c5a0cc7ca
Rebase-Id: R39fb8dac614aeefb1d337c4b5d817038b4ea65d6
Diffstat (limited to 'arch/arm/mach-tegra/timer-t2.c')
| -rw-r--r-- | arch/arm/mach-tegra/timer-t2.c | 27 |
1 files changed, 8 insertions, 19 deletions
diff --git a/arch/arm/mach-tegra/timer-t2.c b/arch/arm/mach-tegra/timer-t2.c index 36ef3fd89bf3..00550aea9e53 100644 --- a/arch/arm/mach-tegra/timer-t2.c +++ b/arch/arm/mach-tegra/timer-t2.c @@ -47,10 +47,10 @@ #define TIMERUS_USEC_CFG 0x14 #define TIMERUS_CNTR_FREEZE 0x4c -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 +#define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE) +#define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE) +#define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE) +#define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE) #define TIMER_PTV 0x0 #define TIMER_PCR 0x4 @@ -74,7 +74,7 @@ static int tegra_timer_set_next_event(unsigned long cycles, u32 reg; reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); + timer_writel(reg, TIMER3_OFFSET + TIMER_PTV); return 0; } @@ -84,12 +84,12 @@ static void tegra_timer_set_mode(enum clock_event_mode mode, { u32 reg; - timer_writel(0, TIMER3_BASE + TIMER_PTV); + timer_writel(0, TIMER3_OFFSET + TIMER_PTV); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: reg = 0xC0000000 | ((1000000/HZ)-1); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); + timer_writel(reg, TIMER3_OFFSET + TIMER_PTV); break; case CLOCK_EVT_MODE_ONESHOT: break; @@ -176,7 +176,7 @@ void read_persistent_clock(struct timespec *ts) static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); + timer_writel(1<<30, TIMER3_OFFSET + TIMER_PCR); evt->event_handler(evt); return IRQ_HANDLED; } @@ -249,17 +249,6 @@ static void __init tegra_init_timer(void) case 26000000: timer_writel(0x0019, TIMERUS_USEC_CFG); break; -#ifndef CONFIG_ARCH_TEGRA_2x_SOC - case 16800000: - timer_writel(0x0453, TIMERUS_USEC_CFG); - break; - case 38400000: - timer_writel(0x04BF, TIMERUS_USEC_CFG); - break; - case 48000000: - timer_writel(0x002F, TIMERUS_USEC_CFG); - break; -#endif default: WARN(1, "Unknown clock rate"); } |