diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-24 13:43:42 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:37 -0800 |
| commit | 19f34e92a84204667d8e694b68bd4ed52b9acef8 (patch) | |
| tree | 48278b0c42d90a8a8c439d8751112f9c8c968ebc /arch/arm/mach-tegra/timer-t3.c | |
| parent | 08df0f1475e492eb77629c55064ebca902733cca (diff) | |
ARM: tegra: timer: Use common chip id functions
Original-Change-Id: Ibf7a37c0751924f0a8de4932d0d31b6fe6c3c4e8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49049
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Rebase-Id: Rfcfb080975c0f844487b91167fc455882f0cb5f4
Diffstat (limited to 'arch/arm/mach-tegra/timer-t3.c')
| -rw-r--r-- | arch/arm/mach-tegra/timer-t3.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/timer-t3.c b/arch/arm/mach-tegra/timer-t3.c index 4e03d02c7ef5..a7eb5b129d4c 100644 --- a/arch/arm/mach-tegra/timer-t3.c +++ b/arch/arm/mach-tegra/timer-t3.c @@ -36,6 +36,7 @@ #include <asm/localtimer.h> #include <asm/sched_clock.h> +#include <mach/hardware.h> #include <mach/iomap.h> #include <mach/irqs.h> @@ -211,10 +212,6 @@ unsigned long tegra3_lp2_timer_remain(void) void __init tegra3_init_timer(u32 *offset, int *irq) { unsigned long rate = clk_measure_input_freq(); -#ifdef CONFIG_PM_SLEEP - void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804; - unsigned long id = readl(chip_id); -#endif switch (rate) { case 12000000: @@ -244,19 +241,9 @@ void __init tegra3_init_timer(u32 *offset, int *irq) #ifdef CONFIG_PM_SLEEP /* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6. */ - if (((id & 0xFF00) >> 8) == 0x30) { -#ifdef CONFIG_TEGRA_SILICON_PLATFORM - if (((id >> 16) & 0xf) == 1) - tegra_lp2wake_irq[3].irq = INT_TMR_SHARED; -#else - void __iomem *emu_rev = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x860; - unsigned long reg = readl(emu_rev); - unsigned long netlist = reg & 0xFFFF; - unsigned long patch = (reg >> 16) & 0xFF; - if ((netlist == 12) && (patch < 14)) + if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) && + (tegra_get_revision() == TEGRA_REVISION_A01)) tegra_lp2wake_irq[3].irq = INT_TMR_SHARED; -#endif - } tegra3_register_wake_timer(0); #endif |