diff options
author | Alex Frid <afrid@nvidia.com> | 2011-05-11 16:01:44 -0700 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:40 -0800 |
commit | 3a5fc7cb03ae52c52837953cf04f8c2b339b8990 (patch) | |
tree | 4bea0340a64fcd9a8399ae4f46065bcbe4383126 /arch/arm/mach-tegra | |
parent | 52284eb729610150d0718b902ada31bef6099b06 (diff) |
ARM: tegra: power: Enable Tegra3 core DVFS
Enable Tegra3 core DVFS with default EDP limit set to 1.2V.
Bug 812738
Bug 826200
Original-Change-Id: If1e9f431729d0dbe6e8c89d9d8b9d5f9d2e8a2bf
Reviewed-on: http://git-master/r/31254
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R3f6a3633f77b33541171c28078401a0fa51b432c
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 10 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 36d55dc7b329..04caa123bbd8 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -59,7 +59,7 @@ unsigned long tegra_lp0_vec_size; unsigned long tegra_grhost_aperture = ~0ul; static bool is_tegra_debug_uart_hsport; -static int pmu_core_edp; +static int pmu_core_edp = 1200; /* default 1.2V EDP limit */ static int board_panel_type; void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; @@ -278,7 +278,9 @@ int get_core_edp(void) static int __init tegra_pmu_core_edp(char *options) { char *p = options; - pmu_core_edp = memparse(p, &p); + int core_edp = memparse(p, &p); + if (core_edp != 0) + pmu_core_edp = core_edp; return 1; } __setup("core_edp_mv=", tegra_pmu_core_edp); diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 804a40c68e02..64d2f15d76b0 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -22,9 +22,10 @@ #include "clock.h" #include "dvfs.h" #include "fuse.h" +#include "board.h" -static bool tegra_dvfs_cpu_disabled = false; -static bool tegra_dvfs_core_disabled = true; +static bool tegra_dvfs_cpu_disabled; +static bool tegra_dvfs_core_disabled; static const int cpu_millivolts[MAX_DVFS_FREQS] = {750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125}; @@ -40,9 +41,6 @@ static const int cpu_speedo_nominal_millivolts[] = /* speedo_id 0, 1, 2 */ { 1125, 1125, 1125 }; -/* FIXME: EDP limit API */ -static int core_edp_limit; - #define KHZ 1000 #define MHZ 1000000 @@ -60,7 +58,6 @@ static struct dvfs_rail tegra3_dvfs_rail_vdd_core = { .max_millivolts = 1300, .min_millivolts = 950, .step = VDD_CPU_BELOW_VDD_CORE_MAX, - .disabled = true, /* FIXME: replace with sysfs control */ }; static struct dvfs_rail *tegra3_dvfs_rails[] = { @@ -333,6 +330,7 @@ static int __init get_cpu_nominal_mv_index( static int __init get_core_nominal_mv_index(int speedo_id) { int i, mv; + int core_edp_limit = get_core_edp(); /* * Start with nominal level for the chips with this speedo_id. Then, |