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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-09-14 08:22:56 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2012-10-03 14:55:57 +0200
commita33c89148ee32833cb930ea4779e6863c9bbc71d (patch)
tree5f63fb800e04f289be83567d75b0c4ed5b461104 /arch/arm/mach-tegra
parent49f91ff5b1083b8350ea0bd8fc1a37d7436b7e5b (diff)
tegra: colibri_t30: initial Toradex Colibri T30 L4T R16 support
Tested on early prototype Colibri T30 V1.0a eMMC module. Known issues: - spurious boot hang after following kernel message [ 5.595219] Timed out waiting for lock bit on pll pll_a - no audio (SGTL5000) support integrated yet - NAND detection/support disabled for now due to boot hang - USB OTG support disabled for now due to boot hang - trying to spawn L4T R16 X driver seems to hang Note: requires uImage with adjusted entry point/load address as follows mkimage -A arm -C none -O linux -T kernel -a 0x82008000 -e 0x82008000 -n 'Linux-3.1.10-colibri_t30' -d zImage uImage
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Kconfig6
-rw-r--r--arch/arm/mach-tegra/Makefile6
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30-memory.c525
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30-panel.c895
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30-pinmux.c638
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30-power.c480
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30.c837
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30.h71
8 files changed, 3458 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 722cba16101a..00e4c30783ef 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -165,6 +165,12 @@ config MACH_CARDHU
help
Support for NVIDIA Cardhu development platform
+config MACH_COLIBRI_T30
+ bool "Toradex Colibri T30 module"
+ depends on ARCH_TEGRA_3x_SOC
+ help
+ Support for Toradex Colibri T30 module on Iris carrier board
+
config MACH_P1852
bool "P1852 board"
depends on ARCH_TEGRA_3x_SOC
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c2d78afc94b1..c1a76685c31d 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -181,6 +181,12 @@ obj-${CONFIG_MACH_CARDHU} += board-cardhu-sensors.o
obj-${CONFIG_MACH_CARDHU} += board-cardhu-memory.o
obj-${CONFIG_MACH_CARDHU} += board-cardhu-powermon.o
+obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30.o
+obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-panel.o
+obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-pinmux.o
+obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-power.o
+obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-memory.o
+
obj-${CONFIG_MACH_KAI} += board-touch-kai-synaptics-spi.o
obj-y += board-touch-raydium_spi.o
diff --git a/arch/arm/mach-tegra/board-colibri_t30-memory.c b/arch/arm/mach-tegra/board-colibri_t30-memory.c
new file mode 100644
index 000000000000..c264cd7b0a24
--- /dev/null
+++ b/arch/arm/mach-tegra/board-colibri_t30-memory.c
@@ -0,0 +1,525 @@
+/*
+ * Copyright (C) 2012 Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "board.h"
+#include "board-colibri_t30.h"
+#include "tegra3_emc.h"
+#include "fuse.h"
+
+static const struct tegra_emc_table colibri_t30_emc_tables_mt41k256m16re_15e[] = {
+ {
+ 0x32, /* Rev 3.2 */
+//ToDo: dblcheck with Max
+#if 1
+ 30000, /* SDRAM frequency [kHz] */
+#else
+ 200000, /* SDRAM frequency [kHz] */
+#endif
+ {
+ 0x0000000a, /* EmcRc */
+ 0x00000033, /* EmcRfc */
+ 0x00000007, /* EmcRas */
+ 0x00000002, /* EmcRp */
+ 0x00000003, /* EmcR2w */
+ 0x00000009, /* EmcW2r */
+ 0x00000005, /* EmcR2p */
+ 0x0000000a, /* EmcW2p */
+ 0x00000002, /* EmcRdRcd */
+ 0x00000002, /* EmcWrRcd */
+ 0x00000003, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000005, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x00000009, /* EmcQSafe */
+ 0x0000000b, /* EmcRdv */
+ 0x000005e9, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x0000017a, /* EmcPreRefreshReqCnt */
+ 0x00000002, /* EmcPdEx2Wr */
+ 0x00000002, /* EmcPdEx2Rd */
+ 0x00000001, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x00000036, /* EmcTxsr */
+ 0x00000134, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x0000000a, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000618, /* EmcTRefBw */
+ 0x00000006, /* EmcQUseExtra */
+ 0x00000004, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00004288, /* EmcFbioCfg5 */
+ 0x004600a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00080000, /* EmcDllXformDqs0 */
+ 0x00080000, /* EmcDllXformDqs1 */
+ 0x00080000, /* EmcDllXformDqs2 */
+ 0x00080000, /* EmcDllXformDqs3 */
+ 0x00080000, /* EmcDllXformDqs4 */
+ 0x00080000, /* EmcDllXformDqs5 */
+ 0x00080000, /* EmcDllXformDqs6 */
+ 0x00080000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00080000, /* EmcDllXformDq0 */
+ 0x00080000, /* EmcDllXformDq1 */
+ 0x00080000, /* EmcDllXformDq2 */
+ 0x00080000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800211c, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f108, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x08000168, /* EmcXm2QUsePadCtrl */
+ 0x08000000, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x000c000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x80000ce6, /* EmcDynSelfRefControl */
+ 0x00000003, /* McEmemArbCfg */
+ 0xc0000024, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000001, /* McEmemArbTimingRp */
+ 0x00000005, /* McEmemArbTimingRc */
+ 0x00000002, /* McEmemArbTimingRas */
+ 0x00000004, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000003, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000001, /* McEmemArbTimingW2W */
+ 0x00000003, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030102, /* McEmemArbDaTurns */
+ 0x00090505, /* McEmemArbDaCovers */
+ 0x76a30906, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff00, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80001221, /* EmcMrs */
+ 0x80100003, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000001, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+ {
+ 0x32, /* Rev 3.2 */
+ 300000, /* SDRAM frequency [kHz] */
+ {
+ 0x00000010, /* EmcRc */
+ 0x0000004d, /* EmcRfc */
+ 0x0000000b, /* EmcRas */
+ 0x00000003, /* EmcRp */
+ 0x00000002, /* EmcR2w */
+ 0x00000008, /* EmcW2r */
+ 0x00000003, /* EmcR2p */
+ 0x00000009, /* EmcW2p */
+ 0x00000003, /* EmcRdRcd */
+ 0x00000002, /* EmcWrRcd */
+ 0x00000002, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000006, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x0000000a, /* EmcQSafe */
+ 0x0000000c, /* EmcRdv */
+ 0x000008e6, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x00000240, /* EmcPreRefreshReqCnt */
+ 0x0000000a, /* EmcPdEx2Wr */
+ 0x00000008, /* EmcPdEx2Rd */
+ 0x00000007, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x000000b4, /* EmcTxsr */
+ 0x00000200, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x00000010, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000927, /* EmcTRefBw */
+ 0x00000007, /* EmcQUseExtra */
+ 0x00000004, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00005288, /* EmcFbioCfg5 */
+ 0x002b00a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00014000, /* EmcDllXformDqs0 */
+ 0x00014000, /* EmcDllXformDqs1 */
+ 0x00014000, /* EmcDllXformDqs2 */
+ 0x00014000, /* EmcDllXformDqs3 */
+ 0x00014000, /* EmcDllXformDqs4 */
+ 0x00014000, /* EmcDllXformDqs5 */
+ 0x00014000, /* EmcDllXformDqs6 */
+ 0x00014000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00020000, /* EmcDllXformDq0 */
+ 0x00020000, /* EmcDllXformDq1 */
+ 0x00020000, /* EmcDllXformDq2 */
+ 0x00020000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800211c, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f508, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x08000168, /* EmcXm2QUsePadCtrl */
+ 0x08000000, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x0172000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x800012db, /* EmcDynSelfRefControl */
+ 0x00000004, /* McEmemArbCfg */
+ 0x80000037, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000001, /* McEmemArbTimingRp */
+ 0x00000007, /* McEmemArbTimingRc */
+ 0x00000004, /* McEmemArbTimingRas */
+ 0x00000007, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000002, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000002, /* McEmemArbTimingW2W */
+ 0x00000005, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030202, /* McEmemArbDaTurns */
+ 0x000a0507, /* McEmemArbDaCovers */
+ 0x70850e08, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff88, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80000321, /* EmcMrs */
+ 0x80100002, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+ {
+ 0x32, /* Rev 3.2 */
+ 333000, /* SDRAM frequency [kHz] */
+ {
+ 0x00000010, /* EmcRc */
+ 0x00000055, /* EmcRfc */
+ 0x0000000c, /* EmcRas */
+ 0x00000004, /* EmcRp */
+ 0x00000006, /* EmcR2w */
+ 0x00000008, /* EmcW2r */
+ 0x00000003, /* EmcR2p */
+ 0x00000009, /* EmcW2p */
+ 0x00000004, /* EmcRdRcd */
+ 0x00000003, /* EmcWrRcd */
+ 0x00000002, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000006, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x0000000a, /* EmcQSafe */
+ 0x0000000c, /* EmcRdv */
+ 0x000009e8, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x0000027e, /* EmcPreRefreshReqCnt */
+ 0x0000000a, /* EmcPdEx2Wr */
+ 0x00000008, /* EmcPdEx2Rd */
+ 0x00000007, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x000000b4, /* EmcTxsr */
+ 0x00000200, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x00000015, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000a28, /* EmcTRefBw */
+ 0x00000000, /* EmcQUseExtra */
+ 0x00000006, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00007088, /* EmcFbioCfg5 */
+ 0x002600a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00014000, /* EmcDllXformDqs0 */
+ 0x00014000, /* EmcDllXformDqs1 */
+ 0x00014000, /* EmcDllXformDqs2 */
+ 0x00014000, /* EmcDllXformDqs3 */
+ 0x00014000, /* EmcDllXformDqs4 */
+ 0x00014000, /* EmcDllXformDqs5 */
+ 0x00014000, /* EmcDllXformDqs6 */
+ 0x00014000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00020000, /* EmcDllXformDq0 */
+ 0x00020000, /* EmcDllXformDq1 */
+ 0x00020000, /* EmcDllXformDq2 */
+ 0x00020000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800013d, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f508, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x080001e8, /* EmcXm2QUsePadCtrl */
+ 0x08000021, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x016a000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x800014d2, /* EmcDynSelfRefControl */
+ 0x00000005, /* McEmemArbCfg */
+ 0x8000003c, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000002, /* McEmemArbTimingRp */
+ 0x00000008, /* McEmemArbTimingRc */
+ 0x00000005, /* McEmemArbTimingRas */
+ 0x0000000a, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000002, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000002, /* McEmemArbTimingW2W */
+ 0x00000005, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030202, /* McEmemArbDaTurns */
+ 0x000b0608, /* McEmemArbDaCovers */
+ 0x70850f09, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff88, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000000, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80000321, /* EmcMrs */
+ 0x80100002, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+//copy of 333 MHz
+ {
+ 0x32, /* Rev 3.2 */
+ 408000, /* SDRAM frequency [kHz] */
+ {
+ 0x00000010, /* EmcRc */
+ 0x00000055, /* EmcRfc */
+ 0x0000000c, /* EmcRas */
+ 0x00000004, /* EmcRp */
+ 0x00000006, /* EmcR2w */
+ 0x00000008, /* EmcW2r */
+ 0x00000003, /* EmcR2p */
+ 0x00000009, /* EmcW2p */
+ 0x00000004, /* EmcRdRcd */
+ 0x00000003, /* EmcWrRcd */
+ 0x00000002, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000006, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x0000000a, /* EmcQSafe */
+ 0x0000000c, /* EmcRdv */
+ 0x000009e8, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x0000027e, /* EmcPreRefreshReqCnt */
+ 0x0000000a, /* EmcPdEx2Wr */
+ 0x00000008, /* EmcPdEx2Rd */
+ 0x00000007, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x000000b4, /* EmcTxsr */
+ 0x00000200, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x00000015, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000a28, /* EmcTRefBw */
+ 0x00000000, /* EmcQUseExtra */
+ 0x00000006, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00007088, /* EmcFbioCfg5 */
+ 0x002600a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00014000, /* EmcDllXformDqs0 */
+ 0x00014000, /* EmcDllXformDqs1 */
+ 0x00014000, /* EmcDllXformDqs2 */
+ 0x00014000, /* EmcDllXformDqs3 */
+ 0x00014000, /* EmcDllXformDqs4 */
+ 0x00014000, /* EmcDllXformDqs5 */
+ 0x00014000, /* EmcDllXformDqs6 */
+ 0x00014000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00020000, /* EmcDllXformDq0 */
+ 0x00020000, /* EmcDllXformDq1 */
+ 0x00020000, /* EmcDllXformDq2 */
+ 0x00020000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800013d, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f508, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x080001e8, /* EmcXm2QUsePadCtrl */
+ 0x08000021, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x016a000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x800014d2, /* EmcDynSelfRefControl */
+ 0x00000005, /* McEmemArbCfg */
+ 0x8000003c, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000002, /* McEmemArbTimingRp */
+ 0x00000008, /* McEmemArbTimingRc */
+ 0x00000005, /* McEmemArbTimingRas */
+ 0x0000000a, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000002, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000002, /* McEmemArbTimingW2W */
+ 0x00000005, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030202, /* McEmemArbDaTurns */
+ 0x000b0608, /* McEmemArbDaCovers */
+ 0x70850f09, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff88, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000000, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80000321, /* EmcMrs */
+ 0x80100002, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+};
+
+int colibri_t30_emc_init(void)
+{
+//27, 54, 108, 416, 533
+//25.5, 51, 102, 408, 533, 750
+//25.5, 51, 102, 204, 533
+ tegra_init_emc(colibri_t30_emc_tables_mt41k256m16re_15e,
+ ARRAY_SIZE(colibri_t30_emc_tables_mt41k256m16re_15e));
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-colibri_t30-panel.c b/arch/arm/mach-tegra/board-colibri_t30-panel.c
new file mode 100644
index 000000000000..4f201edeca86
--- /dev/null
+++ b/arch/arm/mach-tegra/board-colibri_t30-panel.c
@@ -0,0 +1,895 @@
+/*
+ * arch/arm/mach-tegra/board-colibri_t30-panel.c
+ *
+ * Copyright (c) 2012, Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/ion.h>
+#include <linux/tegra_ion.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/earlysuspend.h>
+#include <linux/pwm_backlight.h>
+#include <asm/atomic.h>
+#include <linux/nvhost.h>
+#include <linux/nvmap.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
+#include <mach/smmu.h>
+
+#include "board.h"
+#include "board-colibri_t30.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "tegra3_host1x_devices.h"
+
+/* common pins( backlight ) for all display boards */
+#define colibri_t30_bl_enb TEGRA_GPIO_PV2 /* BL_ON */
+#define colibri_t30_bl_pwm TEGRA_GPIO_PH0
+#define colibri_t30_hdmi_hpd TEGRA_GPIO_PN7 /* HDMI_INT_N */
+
+static struct regulator *colibri_t30_hdmi_reg = NULL;
+static struct regulator *colibri_t30_hdmi_pll = NULL;
+static struct regulator *colibri_t30_hdmi_vddio = NULL;
+
+static atomic_t sd_brightness = ATOMIC_INIT(255);
+
+static struct regulator *colibri_t30_lvds_reg = NULL;
+static struct regulator *colibri_t30_lvds_vdd_bl = NULL;
+static struct regulator *colibri_t30_lvds_vdd_panel = NULL;
+
+static tegra_dc_bl_output colibri_t30_bl_output_measured = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62,
+ 63, 64, 65, 66, 67, 68, 69, 70,
+ 70, 72, 73, 74, 75, 76, 77, 78,
+ 79, 80, 81, 82, 83, 84, 85, 86,
+ 87, 88, 89, 90, 91, 92, 93, 94,
+ 95, 96, 97, 98, 99, 100, 101, 102,
+ 103, 104, 105, 106, 107, 108, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 124, 125, 126,
+ 127, 128, 129, 130, 131, 132, 133, 133,
+ 134, 135, 136, 137, 138, 139, 140, 141,
+ 142, 143, 144, 145, 146, 147, 148, 148,
+ 149, 150, 151, 152, 153, 154, 155, 156,
+ 157, 158, 159, 160, 161, 162, 163, 164,
+ 165, 166, 167, 168, 169, 170, 171, 172,
+ 173, 174, 175, 176, 177, 179, 180, 181,
+ 182, 184, 185, 186, 187, 188, 189, 190,
+ 191, 192, 193, 194, 195, 196, 197, 198,
+ 199, 200, 201, 202, 203, 204, 205, 206,
+ 207, 208, 209, 211, 212, 213, 214, 215,
+ 216, 217, 218, 219, 220, 221, 222, 223,
+ 224, 225, 226, 227, 228, 229, 230, 231,
+ 232, 233, 234, 235, 236, 237, 238, 239,
+ 240, 241, 242, 243, 244, 245, 246, 247,
+ 248, 249, 250, 251, 252, 253, 254, 255
+};
+
+static p_tegra_dc_bl_output bl_output;
+
+static int colibri_t30_backlight_init(struct device *dev) {
+ int ret;
+
+ bl_output = colibri_t30_bl_output_measured;
+
+ if (WARN_ON(ARRAY_SIZE(colibri_t30_bl_output_measured) != 256))
+ pr_err("bl_output array does not have 256 elements\n");
+
+ tegra_gpio_disable(colibri_t30_bl_pwm);
+
+ ret = gpio_request(colibri_t30_bl_enb, "backlight_enb");
+ if (ret < 0)
+ return ret;
+
+ ret = gpio_direction_output(colibri_t30_bl_enb, 1);
+ if (ret < 0)
+ gpio_free(colibri_t30_bl_enb);
+
+ return ret;
+};
+
+static void colibri_t30_backlight_exit(struct device *dev) {
+ /* int ret; */
+ /*ret = gpio_request(colibri_t30_bl_enb, "backlight_enb");*/
+ gpio_set_value(colibri_t30_bl_enb, 0);
+ gpio_free(colibri_t30_bl_enb);
+ tegra_gpio_disable(colibri_t30_bl_enb);
+ return;
+}
+
+static int colibri_t30_backlight_notify(struct device *unused, int brightness)
+{
+ int cur_sd_brightness = atomic_read(&sd_brightness);
+
+ /* Set the backlight GPIO pin mode to 'backlight_enable' */
+ gpio_request(colibri_t30_bl_enb, "backlight_enb");
+ gpio_set_value(colibri_t30_bl_enb, !!brightness);
+
+ /* SD brightness is a percentage, 8-bit value. */
+ brightness = (brightness * cur_sd_brightness) / 255;
+
+ /* Apply any backlight response curve */
+ if (brightness > 255) {
+ pr_info("Error: Brightness > 255!\n");
+ } else {
+ brightness = bl_output[brightness];
+ /* Full brightness when the output is 0. */
+// brightness = 255 - bl_output[brightness];
+ }
+
+ return brightness;
+}
+
+static int colibri_t30_disp1_check_fb(struct device *dev, struct fb_info *info);
+
+static struct platform_pwm_backlight_data colibri_t30_backlight_data = {
+ .pwm_id = 0,
+ .max_brightness = 255,
+ .dft_brightness = 224,
+ .pwm_period_ns = 1000000,
+ .init = colibri_t30_backlight_init,
+ .exit = colibri_t30_backlight_exit,
+ .notify = colibri_t30_backlight_notify,
+ /* Only toggle backlight on fb blank notifications for disp1 */
+ .check_fb = colibri_t30_disp1_check_fb,
+};
+
+static struct platform_device colibri_t30_backlight_device = {
+ .name = "pwm-backlight",
+ .id = -1,
+ .dev = {
+ .platform_data = &colibri_t30_backlight_data,
+ },
+};
+
+static int colibri_t30_panel_enable(void)
+{
+#if 0
+ if (colibri_t30_lvds_reg == NULL) {
+ colibri_t30_lvds_reg = regulator_get(NULL, "vdd_lvds");
+ if (WARN_ON(IS_ERR(colibri_t30_lvds_reg)))
+ pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
+ __func__, PTR_ERR(colibri_t30_lvds_reg));
+ else
+ regulator_enable(colibri_t30_lvds_reg);
+ }
+
+ if (colibri_t30_lvds_vdd_bl == NULL) {
+ colibri_t30_lvds_vdd_bl = regulator_get(NULL, "vdd_backlight");
+ if (WARN_ON(IS_ERR(colibri_t30_lvds_vdd_bl)))
+ pr_err("%s: couldn't get regulator vdd_backlight: %ld\n",
+ __func__, PTR_ERR(colibri_t30_lvds_vdd_bl));
+ else
+ regulator_enable(colibri_t30_lvds_vdd_bl);
+ }
+
+ if (colibri_t30_lvds_vdd_panel == NULL) {
+ colibri_t30_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
+ if (WARN_ON(IS_ERR(colibri_t30_lvds_vdd_panel)))
+ pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
+ __func__, PTR_ERR(colibri_t30_lvds_vdd_panel));
+ else
+ regulator_enable(colibri_t30_lvds_vdd_panel);
+ }
+#endif
+
+ return 0;
+}
+
+static int colibri_t30_panel_disable(void)
+{
+ if (colibri_t30_lvds_reg) {
+ regulator_disable(colibri_t30_lvds_reg);
+ regulator_put(colibri_t30_lvds_reg);
+ colibri_t30_lvds_reg = NULL;
+ }
+
+ if (colibri_t30_lvds_vdd_bl) {
+ regulator_disable(colibri_t30_lvds_vdd_bl);
+ regulator_put(colibri_t30_lvds_vdd_bl);
+ colibri_t30_lvds_vdd_bl = NULL;
+ }
+
+ if (colibri_t30_lvds_vdd_panel) {
+ regulator_disable(colibri_t30_lvds_vdd_panel);
+ regulator_put(colibri_t30_lvds_vdd_panel);
+ colibri_t30_lvds_vdd_panel= NULL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_TEGRA_DC
+static int colibri_t30_hdmi_vddio_enable(void)
+{
+ int ret;
+ if (!colibri_t30_hdmi_vddio) {
+ colibri_t30_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
+ if (IS_ERR_OR_NULL(colibri_t30_hdmi_vddio)) {
+ ret = PTR_ERR(colibri_t30_hdmi_vddio);
+ pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
+ colibri_t30_hdmi_vddio = NULL;
+ return ret;
+ }
+ }
+ ret = regulator_enable(colibri_t30_hdmi_vddio);
+ if (ret < 0) {
+ pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
+ regulator_put(colibri_t30_hdmi_vddio);
+ colibri_t30_hdmi_vddio = NULL;
+ return ret;
+ }
+ return ret;
+}
+
+static int colibri_t30_hdmi_vddio_disable(void)
+{
+ if (colibri_t30_hdmi_vddio) {
+ regulator_disable(colibri_t30_hdmi_vddio);
+ regulator_put(colibri_t30_hdmi_vddio);
+ colibri_t30_hdmi_vddio = NULL;
+ }
+ return 0;
+}
+
+static int colibri_t30_hdmi_enable(void)
+{
+ int ret;
+ if (!colibri_t30_hdmi_reg) {
+ colibri_t30_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
+ if (IS_ERR_OR_NULL(colibri_t30_hdmi_reg)) {
+ pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+ colibri_t30_hdmi_reg = NULL;
+ return PTR_ERR(colibri_t30_hdmi_reg);
+ }
+ }
+ ret = regulator_enable(colibri_t30_hdmi_reg);
+ if (ret < 0) {
+ pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+ return ret;
+ }
+ if (!colibri_t30_hdmi_pll) {
+ colibri_t30_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
+ if (IS_ERR_OR_NULL(colibri_t30_hdmi_pll)) {
+ pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+ colibri_t30_hdmi_pll = NULL;
+ regulator_put(colibri_t30_hdmi_reg);
+ colibri_t30_hdmi_reg = NULL;
+ return PTR_ERR(colibri_t30_hdmi_pll);
+ }
+ }
+ ret = regulator_enable(colibri_t30_hdmi_pll);
+ if (ret < 0) {
+ pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int colibri_t30_hdmi_disable(void)
+{
+ regulator_disable(colibri_t30_hdmi_reg);
+ regulator_put(colibri_t30_hdmi_reg);
+ colibri_t30_hdmi_reg = NULL;
+
+ regulator_disable(colibri_t30_hdmi_pll);
+ regulator_put(colibri_t30_hdmi_pll);
+ colibri_t30_hdmi_pll = NULL;
+ return 0;
+}
+static struct resource colibri_t30_disp1_resources[] = {
+ {
+ .name = "irq",
+ .start = INT_DISPLAY_GENERAL,
+ .end = INT_DISPLAY_GENERAL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "regs",
+ .start = TEGRA_DISPLAY_BASE,
+ .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "fbmem",
+ .start = 0, /* Filled in by colibri_t30_panel_init() */
+ .end = 0, /* Filled in by colibri_t30_panel_init() */
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource colibri_t30_disp2_resources[] = {
+ {
+ .name = "irq",
+ .start = INT_DISPLAY_B_GENERAL,
+ .end = INT_DISPLAY_B_GENERAL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "regs",
+ .start = TEGRA_DISPLAY2_BASE,
+ .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "fbmem",
+ .flags = IORESOURCE_MEM,
+ .start = 0,
+ .end = 0,
+ },
+ {
+ .name = "hdmi_regs",
+ .start = TEGRA_HDMI_BASE,
+ .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+#endif
+
+static struct tegra_dc_mode colibri_t30_panel_modes[] = {
+#if 0
+ {
+//untested
+ .pclk = 9000000,
+ .h_ref_to_sync = 2,
+ .v_ref_to_sync = 2,
+ .h_sync_width = 41,
+ .v_sync_width = 10,
+ .h_back_porch = 2,
+ .v_back_porch = 2,
+ .h_active = 480,
+ .v_active = 272,
+ .h_front_porch = 2,
+ .v_front_porch = 2,
+ },
+ {
+//working
+ .pclk = 25175000,
+ .h_ref_to_sync = 8,
+ .v_ref_to_sync = 2,
+ .h_sync_width = 96,
+ .v_sync_width = 2,
+ .h_back_porch = 48,
+ .v_back_porch = 33,
+ .h_active = 640,
+ .v_active = 480,
+ .h_front_porch = 16,
+ .v_front_porch = 10,
+ },
+ {
+//works but almost half screen sized rectangle covering left side
+ .pclk = 27000000,
+ .h_ref_to_sync = 4,
+ .v_ref_to_sync = 2,
+ .h_sync_width = 10,
+ .v_sync_width = 3,
+ .h_back_porch = 20,
+ .v_back_porch = 3,
+ .h_active = 800,
+ .v_active = 480,
+ .h_front_porch = 70,
+ .v_front_porch = 3,
+ },
+ {
+//working
+ .pclk = 74250000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 40,
+ .v_sync_width = 5,
+ .h_back_porch = 220,
+ .v_back_porch = 20,
+ .h_active = 1280,
+ .v_active = 720,
+ .h_front_porch = 110,
+ .v_front_porch = 5,
+ },
+ {
+//working after uping hdmi resolution down below
+ .pclk = 162000000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 192,
+ .v_sync_width = 3,
+ .h_back_porch = 304,
+ .v_back_porch = 46,
+ .h_active = 1600,
+ .v_active = 1200,
+ .h_front_porch = 64,
+ .v_front_porch = 1,
+ },
+ {
+//shows just black
+ .pclk = 119000000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 32,
+ .v_sync_width = 6,
+ .h_back_porch = 80,
+ .v_back_porch = 21,
+ .h_active = 1680,
+ .v_active = 1050,
+ .h_front_porch = 48,
+ .v_front_porch = 3,
+ },
+#endif
+ {
+//working with hack
+ .pclk = 148500000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 44,
+ .v_sync_width = 5,
+ .h_back_porch = 148,
+ .v_back_porch = 36,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_front_porch = 88,
+ .v_front_porch = 4,
+ },
+#if 0
+ {
+ .pclk = 154000000,
+// .h_ref_to_sync = 1,
+ .h_ref_to_sync = 11,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 32,
+ .v_sync_width = 6,
+ .h_back_porch = 80,
+// .v_back_porch = 25,
+ .v_back_porch = 26,
+ .h_active = 1920,
+ .v_active = 1200,
+ .h_front_porch = 48,
+ .v_front_porch = 3,
+ },
+#endif
+};
+
+static struct tegra_dc_sd_settings colibri_t30_sd_settings = {
+ .enable = 1, /* enabled by default. */
+ .use_auto_pwm = false,
+ .hw_update_delay = 0,
+ .bin_width = -1,
+ .aggressiveness = 1,
+ .phase_in_adjustments = true,
+ .use_vid_luma = false,
+ /* Default video coefficients */
+ .coeff = {5, 9, 2},
+ .fc = {0, 0},
+ /* Immediate backlight changes */
+ .blp = {1024, 255},
+ /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+ /* Default BL TF */
+ .bltf = {
+ {
+ {57, 65, 74, 83},
+ {93, 103, 114, 126},
+ {138, 151, 165, 179},
+ {194, 209, 225, 242},
+ },
+ {
+ {58, 66, 75, 84},
+ {94, 105, 116, 127},
+ {140, 153, 166, 181},
+ {196, 211, 227, 244},
+ },
+ {
+ {60, 68, 77, 87},
+ {97, 107, 119, 130},
+ {143, 156, 170, 184},
+ {199, 215, 231, 248},
+ },
+ {
+ {64, 73, 82, 91},
+ {102, 113, 124, 137},
+ {149, 163, 177, 192},
+ {207, 223, 240, 255},
+ },
+ },
+ /* Default LUT */
+ .lut = {
+ {
+ {250, 250, 250},
+ {194, 194, 194},
+ {149, 149, 149},
+ {113, 113, 113},
+ {82, 82, 82},
+ {56, 56, 56},
+ {34, 34, 34},
+ {15, 15, 15},
+ {0, 0, 0},
+ },
+ {
+ {246, 246, 246},
+ {191, 191, 191},
+ {147, 147, 147},
+ {111, 111, 111},
+ {80, 80, 80},
+ {55, 55, 55},
+ {33, 33, 33},
+ {14, 14, 14},
+ {0, 0, 0},
+ },
+ {
+ {239, 239, 239},
+ {185, 185, 185},
+ {142, 142, 142},
+ {107, 107, 107},
+ {77, 77, 77},
+ {52, 52, 52},
+ {30, 30, 30},
+ {12, 12, 12},
+ {0, 0, 0},
+ },
+ {
+ {224, 224, 224},
+ {173, 173, 173},
+ {133, 133, 133},
+ {99, 99, 99},
+ {70, 70, 70},
+ {46, 46, 46},
+ {25, 25, 25},
+ {7, 7, 7},
+ {0, 0, 0},
+ },
+ },
+ .sd_brightness = &sd_brightness,
+ .bl_device = &colibri_t30_backlight_device,
+};
+
+#ifdef CONFIG_TEGRA_DC
+static struct tegra_fb_data colibri_t30_fb_data = {
+ .win = 0,
+ .xres = 1920,
+ .yres = 1080,
+// .bits_per_pixel = 16,
+ .bits_per_pixel = 32,
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_fb_data colibri_t30_hdmi_fb_data = {
+ .win = 0,
+ .xres = 1920,
+ .yres = 1080,
+ .bits_per_pixel = 32,
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_out colibri_t30_disp2_out = {
+ .type = TEGRA_DC_OUT_HDMI,
+ .flags = TEGRA_DC_OUT_HOTPLUG_HIGH,
+ .parent_clk = "pll_d2_out0",
+
+ .dcc_bus = 3,
+ .hotplug_gpio = colibri_t30_hdmi_hpd,
+
+ .max_pixclock = KHZ2PICOS(148500),
+
+ .align = TEGRA_DC_ALIGN_MSB,
+ .order = TEGRA_DC_ORDER_RED_BLUE,
+
+ .enable = colibri_t30_hdmi_enable,
+ .disable = colibri_t30_hdmi_disable,
+
+ .postsuspend = colibri_t30_hdmi_vddio_disable,
+ .hotplug_init = colibri_t30_hdmi_vddio_enable,
+};
+
+static struct tegra_dc_platform_data colibri_t30_disp2_pdata = {
+ .flags = TEGRA_DC_FLAG_ENABLED,
+ .default_out = &colibri_t30_disp2_out,
+ .fb = &colibri_t30_hdmi_fb_data,
+ .emc_clk_rate = 300000000,
+};
+#endif
+
+static struct tegra_dc_out colibri_t30_disp1_out = {
+ .align = TEGRA_DC_ALIGN_MSB,
+ .order = TEGRA_DC_ORDER_RED_BLUE,
+ .sd_settings = &colibri_t30_sd_settings,
+ .parent_clk = "pll_d_out0",
+#if 0
+//init?
+ .type = TEGRA_DC_OUT_RGB,
+ .depth = 18,
+ .dither = TEGRA_DC_ORDERED_DITHER,
+
+ .modes = colibri_t30_panel_modes,
+ .n_modes = ARRAY_SIZE(colibri_t30_panel_modes),
+
+ .enable = colibri_t30_panel_enable,
+ .disable = colibri_t30_panel_disable,
+#endif
+};
+
+#ifdef CONFIG_TEGRA_DC
+static struct tegra_dc_platform_data colibri_t30_disp1_pdata = {
+ .flags = TEGRA_DC_FLAG_ENABLED,
+ .default_out = &colibri_t30_disp1_out,
+ .emc_clk_rate = 300000000,
+// .fb = &colibri_t30_fb_data,
+};
+
+static struct nvhost_device colibri_t30_disp1_device = {
+ .name = "tegradc",
+ .id = 0,
+ .resource = colibri_t30_disp1_resources,
+ .num_resources = ARRAY_SIZE(colibri_t30_disp1_resources),
+ .dev = {
+ .platform_data = &colibri_t30_disp1_pdata,
+ },
+};
+
+static int colibri_t30_disp1_check_fb(struct device *dev, struct fb_info *info)
+{
+ return info->device == &colibri_t30_disp1_device.dev;
+}
+
+static struct nvhost_device colibri_t30_disp2_device = {
+ .name = "tegradc",
+ .id = 1,
+ .resource = colibri_t30_disp2_resources,
+ .num_resources = ARRAY_SIZE(colibri_t30_disp2_resources),
+ .dev = {
+ .platform_data = &colibri_t30_disp2_pdata,
+ },
+};
+#else
+static int colibri_t30_disp1_check_fb(struct device *dev, struct fb_info *info)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_TEGRA_NVMAP)
+static struct nvmap_platform_carveout colibri_t30_carveouts[] = {
+ [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
+ [1] = {
+ .name = "generic-0",
+ .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC,
+ .base = 0, /* Filled in by colibri_t30_panel_init() */
+ .size = 0, /* Filled in by colibri_t30_panel_init() */
+ .buddy_size = SZ_32K,
+ },
+};
+
+static struct nvmap_platform_data colibri_t30_nvmap_data = {
+ .carveouts = colibri_t30_carveouts,
+ .nr_carveouts = ARRAY_SIZE(colibri_t30_carveouts),
+};
+
+static struct platform_device colibri_t30_nvmap_device = {
+ .name = "tegra-nvmap",
+ .id = -1,
+ .dev = {
+ .platform_data = &colibri_t30_nvmap_data,
+ },
+};
+#endif
+
+#if defined(CONFIG_ION_TEGRA)
+
+static struct platform_device tegra_iommu_device = {
+ .name = "tegra_iommu_device",
+ .id = -1,
+ .dev = {
+ .platform_data = (void *)((1 << HWGRP_COUNT) - 1),
+ },
+};
+
+static struct ion_platform_data tegra_ion_data = {
+ .nr = 4,
+ .heaps = {
+ {
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .id = TEGRA_ION_HEAP_CARVEOUT,
+ .name = "carveout",
+ .base = 0,
+ .size = 0,
+ },
+ {
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .id = TEGRA_ION_HEAP_IRAM,
+ .name = "iram",
+ .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+ .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+ },
+ {
+ .type = ION_HEAP_TYPE_CARVEOUT,
+ .id = TEGRA_ION_HEAP_VPR,
+ .name = "vpr",
+ .base = 0,
+ .size = 0,
+ },
+ {
+ .type = ION_HEAP_TYPE_IOMMU,
+ .id = TEGRA_ION_HEAP_IOMMU,
+ .name = "iommu",
+ .base = TEGRA_SMMU_BASE,
+ .size = TEGRA_SMMU_SIZE,
+ .priv = &tegra_iommu_device.dev,
+ },
+ },
+};
+
+static struct platform_device tegra_ion_device = {
+ .name = "ion-tegra",
+ .id = -1,
+ .dev = {
+ .platform_data = &tegra_ion_data,
+ },
+};
+#endif
+
+static struct platform_device *colibri_t30_gfx_devices[] __initdata = {
+#if defined(CONFIG_TEGRA_NVMAP)
+ &colibri_t30_nvmap_device,
+#endif
+#if defined(CONFIG_ION_TEGRA)
+ &tegra_ion_device,
+#endif
+ &tegra_pwfm0_device,
+ &colibri_t30_backlight_device,
+};
+
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+/* put early_suspend/late_resume handlers here for the display in order
+ * to keep the code out of the display driver, keeping it closer to upstream
+ */
+struct early_suspend colibri_t30_panel_early_suspender;
+
+static void colibri_t30_panel_early_suspend(struct early_suspend *h)
+{
+ /* power down LCD, add use a black screen for HDMI */
+ if (num_registered_fb > 0)
+ fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
+ if (num_registered_fb > 1)
+ fb_blank(registered_fb[1], FB_BLANK_NORMAL);
+}
+
+static void colibri_t30_panel_late_resume(struct early_suspend *h)
+{
+ unsigned i;
+ for (i = 0; i < num_registered_fb; i++)
+ fb_blank(registered_fb[i], FB_BLANK_UNBLANK);
+}
+#endif
+
+static void colibri_t30_panel_preinit(void)
+{
+ colibri_t30_disp1_out.parent_clk_backup = "pll_d2_out0";
+ colibri_t30_disp1_out.type = TEGRA_DC_OUT_RGB;
+ colibri_t30_disp1_out.depth = 18;
+ colibri_t30_disp1_out.dither = TEGRA_DC_ORDERED_DITHER;
+ colibri_t30_disp1_out.modes = colibri_t30_panel_modes;
+ colibri_t30_disp1_out.n_modes = ARRAY_SIZE(colibri_t30_panel_modes);
+ colibri_t30_disp1_out.enable = colibri_t30_panel_enable;
+ colibri_t30_disp1_out.disable = colibri_t30_panel_disable;
+
+ colibri_t30_disp1_pdata.fb = &colibri_t30_fb_data;
+}
+
+int __init colibri_t30_panel_init(void)
+{
+ int err = 0;
+ struct resource *res;
+
+#if defined(CONFIG_TEGRA_NVMAP)
+ colibri_t30_carveouts[1].base = tegra_carveout_start;
+ colibri_t30_carveouts[1].size = tegra_carveout_size;
+#endif
+
+#if defined(CONFIG_ION_TEGRA)
+ tegra_ion_data.heaps[0].base = tegra_carveout_start;
+ tegra_ion_data.heaps[0].size = tegra_carveout_size;
+#endif
+
+ colibri_t30_panel_preinit();
+
+#if defined(CONFIG_TEGRA_DC)
+ /* initialize the values */
+#if defined(PM313_LVDS_PANEL_19X12)
+ colibri_t30_disp1_out.modes = panel_19X12_modes;
+ colibri_t30_disp1_out.n_modes = ARRAY_SIZE(panel_19X12_modes);
+ colibri_t30_disp1_out.parent_clk = "pll_d_out0";
+ colibri_t30_disp1_out.depth = 18;
+// colibri_t30_disp1_out.depth = 24;
+ colibri_t30_fb_data.xres = 1920;
+ colibri_t30_fb_data.yres = 1200;
+
+ colibri_t30_disp2_out.parent_clk = "pll_d2_out0";
+ colibri_t30_hdmi_fb_data.xres = 1920;
+ colibri_t30_hdmi_fb_data.yres = 1200;
+#endif
+
+// err = gpio_request(pm313_lvds_shutdown, "lvds_shutdown");
+ /* free ride provided by bootloader */
+// err |= gpio_direction_output(pm313_lvds_shutdown, 1);
+
+ if (err)
+ printk(KERN_ERR "ERROR(s) in LVDS configuration\n");
+#endif
+
+ gpio_request(colibri_t30_hdmi_hpd, "hdmi_hpd");
+ gpio_direction_input(colibri_t30_hdmi_hpd);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+ colibri_t30_panel_early_suspender.suspend = colibri_t30_panel_early_suspend;
+ colibri_t30_panel_early_suspender.resume = colibri_t30_panel_late_resume;
+ colibri_t30_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
+ register_early_suspend(&colibri_t30_panel_early_suspender);
+#endif
+
+#ifdef CONFIG_TEGRA_GRHOST
+ err = tegra3_register_host1x_devices();
+ if (err)
+ return err;
+#endif
+
+ err = platform_add_devices(colibri_t30_gfx_devices,
+ ARRAY_SIZE(colibri_t30_gfx_devices));
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+ res = nvhost_get_resource_byname(&colibri_t30_disp1_device,
+ IORESOURCE_MEM, "fbmem");
+ res->start = tegra_fb_start;
+ res->end = tegra_fb_start + tegra_fb_size - 1;
+#endif
+
+ /* Copy the bootloader fb to the fb. */
+ tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
+ min(tegra_fb_size, tegra_bootloader_fb_size));
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+ if (!err)
+ err = nvhost_device_register(&colibri_t30_disp1_device);
+
+ res = nvhost_get_resource_byname(&colibri_t30_disp2_device,
+ IORESOURCE_MEM, "fbmem");
+ res->start = tegra_fb2_start;
+ res->end = tegra_fb2_start + tegra_fb2_size - 1;
+
+ /* Copy the bootloader fb to the fb2. */
+ tegra_move_framebuffer(tegra_fb2_start, tegra_bootloader_fb_start,
+ min(tegra_fb2_size, tegra_bootloader_fb_size));
+
+ if (!err)
+ err = nvhost_device_register(&colibri_t30_disp2_device);
+#endif
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
+ if (!err)
+ err = nvhost_device_register(&nvavp_device);
+#endif
+ return err;
+}
diff --git a/arch/arm/mach-tegra/board-colibri_t30-pinmux.c b/arch/arm/mach-tegra/board-colibri_t30-pinmux.c
new file mode 100644
index 000000000000..d6375d6df168
--- /dev/null
+++ b/arch/arm/mach-tegra/board-colibri_t30-pinmux.c
@@ -0,0 +1,638 @@
+/*
+ * arch/arm/mach-tegra/board-colibri_t30-pinmux.c
+ *
+ * Copyright (C) 2012 Toradex, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <mach/pinmux.h>
+
+#include "board-colibri_t30.h"
+#include "board.h"
+#include "gpio-names.h"
+
+#define DEFAULT_DRIVE(_name) \
+ { \
+ .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
+ .hsm = TEGRA_HSM_DISABLE, \
+ .schmitt = TEGRA_SCHMITT_ENABLE, \
+ .drive = TEGRA_DRIVE_DIV_1, \
+ .pull_down = TEGRA_PULL_31, \
+ .pull_up = TEGRA_PULL_31, \
+ .slew_rising = TEGRA_SLEW_SLOWEST, \
+ .slew_falling = TEGRA_SLEW_SLOWEST, \
+ }
+
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ * strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive
+ * strength code. Value from 0 to 31.
+ * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code
+ * code 11 is least slewing of signal. code 00 is highest
+ * slewing of the signal.
+ * Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew - Driver Output Pull-Down slew control code -
+ * code 11 is least slewing of signal. code 00 is highest
+ * slewing of the signal.
+ * Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+ { \
+ .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \
+ .hsm = TEGRA_HSM_##_hsm, \
+ .schmitt = TEGRA_SCHMITT_##_schmitt, \
+ .drive = TEGRA_DRIVE_##_drive, \
+ .pull_down = TEGRA_PULL_##_pulldn_drive, \
+ .pull_up = TEGRA_PULL_##_pullup_drive, \
+ .slew_rising = TEGRA_SLEW_##_pulldn_slew, \
+ .slew_falling = TEGRA_SLEW_##_pullup_slew, \
+ }
+
+static __initdata struct tegra_drive_pingroup_config colibri_t30_drive_pinmux[] = {
+ /* DEFAULT_DRIVE(<pin_group>), */
+ SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* All I2C pins are driven to maximum drive strength */
+
+ /* GEN1 I2C */
+ SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* DDC I2C */
+ SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* PWR_I2C */
+ SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* UART3 */
+ SET_DRIVE(UART3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+ /* SDMMC2 */
+ SET_DRIVE(SDIO2, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+
+ /* SDMMC4 */
+ SET_DRIVE(GMA, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+ SET_DRIVE(GMB, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+ SET_DRIVE(GMC, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+ SET_DRIVE(GMD, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+};
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \
+ { \
+ .pingroup = TEGRA_PINGROUP_##_pingroup, \
+ .func = TEGRA_MUX_##_mux, \
+ .pupd = TEGRA_PUPD_##_pupd, \
+ .tristate = TEGRA_TRI_##_tri, \
+ .io = TEGRA_PIN_##_io, \
+ .lock = TEGRA_PIN_LOCK_DEFAULT, \
+ .od = TEGRA_PIN_OD_DEFAULT, \
+ .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = TEGRA_PINGROUP_##_pingroup, \
+ .func = TEGRA_MUX_##_mux, \
+ .pupd = TEGRA_PUPD_##_pupd, \
+ .tristate = TEGRA_TRI_##_tri, \
+ .io = TEGRA_PIN_##_io, \
+ .lock = TEGRA_PIN_LOCK_##_lock, \
+ .od = TEGRA_PIN_OD_##_od, \
+ .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = TEGRA_PINGROUP_##_pingroup, \
+ .func = TEGRA_MUX_##_mux, \
+ .pupd = TEGRA_PUPD_##_pupd, \
+ .tristate = TEGRA_TRI_##_tri, \
+ .io = TEGRA_PIN_##_io, \
+ .lock = TEGRA_PIN_LOCK_##_lock, \
+ .od = TEGRA_PIN_OD_DEFAULT, \
+ .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \
+ }
+
+static __initdata struct tegra_pingroup_config colibri_t30_pinmux[] = {
+//multiplexed KB_ROW_13
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(CAM_I2C_SCL, POPSDMMC4, PULL_UP, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, TRISTATE, INPUT),
+#endif
+//multiplexed KB_ROW_14
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(CAM_I2C_SDA, POPSDMMC4, PULL_UP, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, TRISTATE, INPUT),
+#endif
+
+//multiplexed KB_ROW_10
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, TRISTATE, INPUT),
+#endif
+
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(CLK3_OUT, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, TRISTATE, OUTPUT),
+
+ DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(DAP1_FS, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK, GMI, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(DAP2_FS, RSVD2, NORMAL, NORMAL, INPUT),
+
+//NC
+ DEFAULT_PINMUX(DAP2_DIN, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, RSVD2, NORMAL, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(DAP2_SCLK, RSVD2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(DAP4_DIN, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, RSVD1, NORMAL, NORMAL, INPUT),
+
+ I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(GEN2_I2C_SCL, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GEN2_I2C_SDA, RSVD3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD9, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD10, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD11, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD14, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD15, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS0_N, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS1_N, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS6_N, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_WAIT, NAND, NORMAL, NORMAL, INPUT),
+//GPIO C7: eMMC vs. NAND flash detection
+ DEFAULT_PINMUX(GMI_WP_N, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, NORMAL, OUTPUT),
+//???
+ DEFAULT_PINMUX(GMI_RST_N, GMI, NORMAL, NORMAL, OUTPUT),
+
+//multiplexed KB_ROW_12
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(GPIO_PBB0, POPSDMMC4, PULL_UP, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, TRISTATE, INPUT),
+#endif
+//multiplexed KB_ROW_15
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(GPIO_PBB3, POPSDMMC4, PULL_UP, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, TRISTATE, INPUT),
+#endif
+ DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+//multiplexed KB_ROW_11
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, PULL_UP, NORMAL, INPUT),
+#else
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+#endif
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+#endif
+
+ DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
+//GPIO U6: MM_CD
+ DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+
+//GPIO V0: touch pendown int
+ DEFAULT_PINMUX(GPIO_PV0, RSVD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, OUTPUT),
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, TRISTATE, OUTPUT),
+#else
+//GPIO V2: BL_ON
+ DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+#endif
+
+ DEFAULT_PINMUX(HDMI_CEC, RSVD1, NORMAL, TRISTATE, INPUT),
+//GPIO N7: HOTPLUG_DETECT
+ DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+//all tristate?
+ DEFAULT_PINMUX(KB_COL0, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL3, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL4, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW0, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW4, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9, KBC, NORMAL, TRISTATE, INPUT),
+
+//multiplexed SDMMC4.B
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW11, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW15, KBC, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(KB_ROW10, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11, SDMMC2, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12, SDMMC2, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, SDMMC2, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, SDMMC2, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15, SDMMC2, PULL_UP, NORMAL, INPUT),
+#endif
+
+ DEFAULT_PINMUX(LCD_CS0_N, RSVD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0, RSVD1, NORMAL, NORMAL, INPUT),
+//GPIO D2: THERMD_ALERT_N
+ DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, INPUT),
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(LCD_PWR1, RSVD1, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(LCD_PWR1, RSVD1, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN, RSVD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, TRISTATE, INPUT),
+
+//GPIO DD2: LAN_VBUS
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+//GPIO DD0: LAN_RESET
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+//GPIO DD1: LAN_EXTWAKEUP
+ DEFAULT_PINMUX(PEX_L0_RST_N, RSVD2, NORMAL, NORMAL, INPUT),
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD2, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD2, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD2, NORMAL, TRISTATE, INPUT),
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(PEX_L1_RST_N, RSVD2, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, RSVD2, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(PEX_L1_RST_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, RSVD2, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N, RSVD2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+//GPIO DD3: LAN_PME
+ DEFAULT_PINMUX(PEX_WAKE_N, RSVD2, NORMAL, NORMAL, INPUT),
+
+/* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(SDMMC1_CLK, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, RSVD1, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(SDMMC1_CLK, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, RSVD1, NORMAL, NORMAL, INPUT),
+#endif
+
+ DEFAULT_PINMUX(SDMMC3_CLK, PWM2, NORMAL, NORMAL, INPUT),
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(SDMMC3_CMD, PWM3, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(SDMMC3_CMD, PWM3, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(SDMMC3_DAT0, RSVD0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, RSVD0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, PWM1, NORMAL, NORMAL, INPUT),
+#ifdef COLIBRI_T30_VI
+ DEFAULT_PINMUX(SDMMC3_DAT3, PWM0, NORMAL, TRISTATE, INPUT),
+#else
+ DEFAULT_PINMUX(SDMMC3_DAT3, PWM0, NORMAL, NORMAL, INPUT),
+#endif
+ DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, TRISTATE, INPUT),
+//multiplexed ULPI_STP used as SSPFRM
+ DEFAULT_PINMUX(SDMMC3_DAT6, SPDIF, NORMAL, TRISTATE, INPUT),
+//multiplexed ULPI_CLK used as SSPTXD
+ DEFAULT_PINMUX(SDMMC3_DAT7, SPDIF, NORMAL, TRISTATE, OUTPUT),
+
+//eMMC
+#ifdef COLIBRI_T30_SDMMC4B
+ DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, NORMAL, TRISTATE, INPUT),
+#else /* COLIBRI_T30_SDMMC4B */
+ DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT),
+// DEFAULT_PINMUX(SDMMC4_RST_N, SDMMC4, PULL_DOWN, NORMAL, INPUT),
+#endif /* COLIBRI_T30_SDMMC4B */
+
+//GPIO K6: USB_ID, multiplexed ACC1_DETECT
+ DEFAULT_PINMUX(SPDIF_IN, HDA, NORMAL, NORMAL, INPUT),
+//GPIO K5: USBC_DET(VBUS), multiplexed USB1_VBUS
+ DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI2_CS0_N, SPI2, NORMAL, NORMAL, INPUT),
+//GPIO W2: USBH_PEN
+ DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, OUTPUT),
+//GPIO W3: USBH_OC
+ DEFAULT_PINMUX(SPI2_CS2_N, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_MISO, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_MOSI, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, TRISTATE, OUTPUT),
+
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(UART3_TXD, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+//multiplexed SDMMC3_DAT7
+ DEFAULT_PINMUX(ULPI_CLK, SPI1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
+//multiplexed SDMMC3_DAT6
+ DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, OUTPUT),
+
+ VI_PINMUX(VI_D0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D10, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_D11, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ VI_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+//GPIO T1: EN_MIC_GND
+ DEFAULT_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, OUTPUT),
+ VI_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static __initdata struct tegra_pingroup_config colibri_t30_unused_pins_lowpower[] = {
+//required?
+};
+
+#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \
+ { \
+ .gpio_nr = _gpio, \
+ .is_input = _is_input, \
+ .value = _value, \
+ }
+
+static struct gpio_init_pin_info colibri_t30_init_gpio_mode[] = {
+ GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD6, false, 0),
+ GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD4, false, 0),
+};
+
+static void __init colibri_t30_gpio_init_configure(void)
+{
+ int len;
+ int i;
+ struct gpio_init_pin_info *pins_info;
+
+ len = ARRAY_SIZE(colibri_t30_init_gpio_mode);
+ pins_info = colibri_t30_init_gpio_mode;
+
+ for (i = 0; i < len; ++i) {
+ tegra_gpio_init_configure(pins_info->gpio_nr,
+ pins_info->is_input,
+ pins_info->value);
+ pins_info++;
+ }
+}
+
+int __init colibri_t30_pinmux_init(void)
+{
+ colibri_t30_gpio_init_configure();
+
+ tegra_pinmux_config_table(colibri_t30_pinmux,
+ ARRAY_SIZE(colibri_t30_pinmux));
+ tegra_drive_pinmux_config_table(colibri_t30_drive_pinmux,
+ ARRAY_SIZE(colibri_t30_drive_pinmux));
+
+ tegra_pinmux_config_table(colibri_t30_unused_pins_lowpower,
+ ARRAY_SIZE(colibri_t30_unused_pins_lowpower));
+
+ return 0;
+}
+
+#define PIN_GPIO_LPM(_name, _gpio, _is_input, _value) \
+ { \
+ .name = _name, \
+ .gpio_nr = _gpio, \
+ .is_gpio = true, \
+ .is_input = _is_input, \
+ .value = _value, \
+ }
+
+struct gpio_init_pin_info colibri_t30_pin_lpm[] = {
+//required?
+};
+
+static void set_unused_pin_gpio(struct gpio_init_pin_info *lpm_pin_info,
+ int list_count)
+{
+ int i;
+ struct gpio_init_pin_info *pin_info;
+ int ret;
+
+ for (i = 0; i < list_count; ++i) {
+ pin_info = (struct gpio_init_pin_info *)(lpm_pin_info + i);
+ if (!pin_info->is_gpio)
+ continue;
+
+ ret = gpio_request(pin_info->gpio_nr, pin_info->name);
+ if (ret < 0) {
+ pr_err("%s() Error in gpio_request() for gpio %d\n",
+ __func__, pin_info->gpio_nr);
+ continue;
+ }
+ if (pin_info->is_input)
+ ret = gpio_direction_input(pin_info->gpio_nr);
+ else
+ ret = gpio_direction_output(pin_info->gpio_nr,
+ pin_info->value);
+ if (ret < 0) {
+ pr_err("%s() Error in setting gpio %d to in/out\n",
+ __func__, pin_info->gpio_nr);
+ gpio_free(pin_info->gpio_nr);
+ continue;
+ }
+ tegra_gpio_enable(pin_info->gpio_nr);
+ }
+}
+
+/* Initialize the pins to desired state as per power/asic/system-eng
+ * recomendation */
+int __init colibri_t30_pins_state_init(void)
+{
+ set_unused_pin_gpio(&colibri_t30_pin_lpm[0],
+ ARRAY_SIZE(colibri_t30_pin_lpm));
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-colibri_t30-power.c b/arch/arm/mach-tegra/board-colibri_t30-power.c
new file mode 100644
index 000000000000..b5ad7956277c
--- /dev/null
+++ b/arch/arm/mach-tegra/board-colibri_t30-power.c
@@ -0,0 +1,480 @@
+/*
+ * arch/arm/mach-tegra/board-colibri_t30-power.c
+ *
+ * Copyright (C) 2012 Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <asm/mach-types.h>
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/mfd/max77663-core.h>
+#include <linux/mfd/tps6591x.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+//#include <linux/power/gpio-charger.h>
+#include <linux/regulator/fixed.h>
+//#include <linux/regulator/gpio-switch-regulator.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/tps62360.h>
+#include <linux/regulator/tps6591x-regulator.h>
+#include <linux/resource.h>
+
+#include <mach/edp.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+//#include <mach/suspend.h>
+
+#include "board-colibri_t30.h"
+#include "board.h"
+#include "gpio-names.h"
+#include "tegra3_tsensor.h"
+#include "pm.h"
+#include "wakeups.h"
+#include "wakeups-t3.h"
+
+#define PMC_CTRL 0x0
+#define PMC_CTRL_INTR_LOW (1 << 17)
+
+/* SW1: unused */
+static struct regulator_consumer_supply tps6591x_vdd1_supply_0[] = {
+REGULATOR_SUPPLY("unused_rail_vdd1", NULL),
+// REGULATOR_SUPPLY("en_vddio_ddr_1v2", NULL),
+};
+
+/* SW2: +V1.35_VDDIO_DDR */
+static struct regulator_consumer_supply tps6591x_vdd2_supply_0[] = {
+REGULATOR_SUPPLY("mem_vddio_ddr", NULL),
+REGULATOR_SUPPLY("t30_vddio_ddr", NULL),
+};
+
+/* SW: +V1.0_VDD_CPU */
+static struct regulator_consumer_supply tps6591x_vddctrl_supply_0[] = {
+ REGULATOR_SUPPLY("vdd_cpu_pmu", NULL),
+REGULATOR_SUPPLY("vdd_cpu", NULL),
+//!=vddio_sys!
+ REGULATOR_SUPPLY("vdd_sys", NULL),
+};
+
+/* SWIO: +V1.8 */
+static struct regulator_consumer_supply tps6591x_vio_supply_0[] = {
+ REGULATOR_SUPPLY("vdd_gen1v8", NULL),
+ REGULATOR_SUPPLY("avdd_usb_pll", NULL),
+ REGULATOR_SUPPLY("avdd_osc", NULL),
+ REGULATOR_SUPPLY("vddio_sys", NULL),
+ REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+ REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
+ REGULATOR_SUPPLY("vdd1v8_satelite", NULL),
+ REGULATOR_SUPPLY("vddio_uart", NULL),
+ REGULATOR_SUPPLY("pwrdet_uart", NULL),
+ REGULATOR_SUPPLY("vddio_audio", NULL),
+ REGULATOR_SUPPLY("pwrdet_audio", NULL),
+ REGULATOR_SUPPLY("vddio_bb", NULL),
+ REGULATOR_SUPPLY("pwrdet_bb", NULL),
+ REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
+ REGULATOR_SUPPLY("pwrdet_lcd", NULL),
+ REGULATOR_SUPPLY("vddio_cam", NULL),
+ REGULATOR_SUPPLY("pwrdet_cam", NULL),
+ REGULATOR_SUPPLY("vddio_vi", NULL),
+ REGULATOR_SUPPLY("pwrdet_vi", NULL),
+ REGULATOR_SUPPLY("ldo6", NULL),
+ REGULATOR_SUPPLY("ldo7", NULL),
+ REGULATOR_SUPPLY("ldo8", NULL),
+ REGULATOR_SUPPLY("vcore_audio", NULL),
+ REGULATOR_SUPPLY("avcore_audio", NULL),
+ REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.1"),
+ REGULATOR_SUPPLY("pwrdet_sdmmc2", NULL),
+ REGULATOR_SUPPLY("vcore1_lpddr2", NULL),
+ REGULATOR_SUPPLY("vcom_1v8", NULL),
+ REGULATOR_SUPPLY("pmuio_1v8", NULL),
+ REGULATOR_SUPPLY("avdd_ic_usb", NULL),
+};
+
+/* +V1.05_AVDD_PLLE */
+static struct regulator_consumer_supply tps6591x_ldo1_supply_0[] = {
+REGULATOR_SUPPLY("avdd_plle", NULL),
+};
+
+/* EN_+V3.3 switching via FET: +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
++V3.3:
+VDD_DDR_RX
+VDDIO_LCD_1
+VDDIO_LCD_2
+VDDIO_CAM
+LM95245
+VDDIO_SYS_01
+VDDIO_SYS_02
+VDDIO_BB
+VDDIO_AUDIO
+VDDIO_GMI_1
+VDDIO_GMI_2
+VDDIO_GMI_3
+VDDIO_UART
+VDDIO_SDMMC1
+AVDD_USB
+VDDIO_SDMMC3
+74AVCAH164245
+VDDIO_PEX_CTL
+TPS65911 VDDIO
+MT29F16G08
+SGTL5000 VDDIO
+STMPE811
+AX88772B VCC3x
+SDIN5D2-2G VCCx */
+static struct regulator_consumer_supply tps6591x_ldo2_supply_0[] = {
+REGULATOR_SUPPLY("avdd_audio", NULL),
+REGULATOR_SUPPLY("avdd_usb", NULL),
+ REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"),
+};
+
+/* unused */
+static struct regulator_consumer_supply tps6591x_ldo3_supply_0[] = {
+REGULATOR_SUPPLY("unused_rail_ldo3", NULL),
+};
+
+/* +V1.2_VDD_RTC */
+static struct regulator_consumer_supply tps6591x_ldo4_supply_0[] = {
+REGULATOR_SUPPLY("vdd_rtc", NULL),
+};
+
+/* +V2.8_AVDD_VDAC */
+//only required for analog RGB
+static struct regulator_consumer_supply tps6591x_ldo5_supply_0[] = {
+REGULATOR_SUPPLY("avdd_vdac", NULL),
+};
+
+/* unused */
+static struct regulator_consumer_supply tps6591x_ldo6_supply_0[] = {
+REGULATOR_SUPPLY("unused_rail_ldo6", NULL),
+};
+
+/* +V1.2_AVDD_PLL */
+static struct regulator_consumer_supply tps6591x_ldo7_supply_0[] = {
+ REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
+ REGULATOR_SUPPLY("avdd_pllm", NULL),
+ REGULATOR_SUPPLY("avdd_pllu_d", NULL),
+ REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
+ REGULATOR_SUPPLY("avdd_pllx", NULL),
+};
+
+/* +V1.0_VDD_DDR_HS */
+static struct regulator_consumer_supply tps6591x_ldo8_supply_0[] = {
+REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
+};
+
+#define TPS_PDATA_INIT(_name, _sname, _minmv, _maxmv, _supply_reg, _always_on, \
+ _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, _ectrl, _flags) \
+ static struct tps6591x_regulator_platform_data pdata_##_name##_##_sname = \
+ { \
+ .regulator = { \
+ .constraints = { \
+ .min_uV = (_minmv)*1000, \
+ .max_uV = (_maxmv)*1000, \
+ .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
+ REGULATOR_MODE_STANDBY), \
+ .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
+ REGULATOR_CHANGE_STATUS | \
+ REGULATOR_CHANGE_VOLTAGE), \
+ .always_on = _always_on, \
+ .boot_on = _boot_on, \
+ .apply_uV = _apply_uv, \
+ }, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(tps6591x_##_name##_supply_##_sname), \
+ .consumer_supplies = tps6591x_##_name##_supply_##_sname, \
+ .supply_regulator = _supply_reg, \
+ }, \
+ .init_uV = _init_uV * 1000, \
+ .init_enable = _init_enable, \
+ .init_apply = _init_apply, \
+ .ectrl = _ectrl, \
+ .flags = _flags, \
+ }
+
+TPS_PDATA_INIT(vdd1, 0, 600, 1500, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, 0);
+TPS_PDATA_INIT(vdd2, 0, 1350, 1350, 0, 0, 1, 0, -1, 0, 0, 0, 0);
+TPS_PDATA_INIT(vddctrl, 0, 600, 1400, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1, 0);
+TPS_PDATA_INIT(vio, 0, 1500, 3300, 0, 1, 1, 0, -1, 0, 0, 0, 0);
+
+TPS_PDATA_INIT(ldo1, 0, 1000, 3300, tps6591x_rails(VDD_2), 0, 0, 0, -1, 0, 1, 0, 0);
+/* Make sure EN_+V3.3 is always on! */
+TPS_PDATA_INIT(ldo2, 0, 1200, 1200, tps6591x_rails(VDD_2), 1, 1, 1, -1, 0, 1, 0, 0);
+
+TPS_PDATA_INIT(ldo3, 0, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0);
+TPS_PDATA_INIT(ldo4, 0, 1000, 3300, 0, 1, 0, 0, -1, 0, 0, 0, LDO_LOW_POWER_ON_SUSPEND);
+TPS_PDATA_INIT(ldo5, 0, 2800, 2800, 0, 0, 0, 0, -1, 0, 0, 0, 0);
+
+TPS_PDATA_INIT(ldo6, 0, 1200, 1200, tps6591x_rails(VIO), 0, 0, 1, -1, 0, 0, 0, 0);
+TPS_PDATA_INIT(ldo7, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND);
+TPS_PDATA_INIT(ldo8, 0, 1000, 3300, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND);
+
+#if defined(CONFIG_RTC_DRV_TPS6591x)
+static struct tps6591x_rtc_platform_data rtc_data = {
+ .irq = TEGRA_NR_IRQS + TPS6591X_INT_RTC_ALARM,
+ .time = {
+ .tm_year = 2000,
+ .tm_mon = 0,
+ .tm_mday = 1,
+ .tm_hour = 0,
+ .tm_min = 0,
+ .tm_sec = 0,
+ },
+};
+
+#define TPS_RTC_REG() \
+ { \
+ .id = 0, \
+ .name = "rtc_tps6591x", \
+ .platform_data = &rtc_data, \
+ }
+#endif
+
+#define TPS_REG(_id, _name, _sname) \
+ { \
+ .id = TPS6591X_ID_##_id, \
+ .name = "tps6591x-regulator", \
+ .platform_data = &pdata_##_name##_##_sname, \
+ }
+
+static struct tps6591x_subdev_info colibri_t30_tps_devs[] = {
+ TPS_REG(VDD_1, vdd1, 0),
+ TPS_REG(VDD_2, vdd2, 0),
+ TPS_REG(VDDCTRL, vddctrl, 0),
+ TPS_REG(VIO, vio, 0),
+ TPS_REG(LDO_1, ldo1, 0),
+ TPS_REG(LDO_2, ldo2, 0),
+ TPS_REG(LDO_3, ldo3, 0),
+ TPS_REG(LDO_4, ldo4, 0),
+ TPS_REG(LDO_5, ldo5, 0),
+ TPS_REG(LDO_6, ldo6, 0),
+ TPS_REG(LDO_7, ldo7, 0),
+ TPS_REG(LDO_8, ldo8, 0),
+#if defined(CONFIG_RTC_DRV_TPS6591x)
+ TPS_RTC_REG(),
+#endif
+};
+
+static struct tps6591x_sleep_keepon_data tps_slp_keepon = {
+ .clkout32k_keepon = 1,
+};
+
+static struct tps6591x_platform_data tps_platform = {
+ .irq_base = TPS6591X_IRQ_BASE,
+ .gpio_base = TPS6591X_GPIO_BASE,
+ .dev_slp_en = true,
+ .slp_keepon = &tps_slp_keepon,
+ .use_power_off = true,
+};
+
+static struct i2c_board_info __initdata colibri_t30_regulators[] = {
+ {
+ I2C_BOARD_INFO("tps6591x", 0x2D),
+ .irq = INT_EXTERNAL_PMU,
+ .platform_data = &tps_platform,
+ },
+};
+
+/* TPS62362 DC-DC converter
+ SW: +V1.2_VDD_CORE
+ Note: Colibri T30 V1.0 have TPS62360 with different voltage levels at startup */
+static struct regulator_consumer_supply tps6236x_dcdc_supply[] = {
+ REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct tps62360_regulator_platform_data tps6236x_pdata = {
+ .reg_init_data = { \
+ .constraints = { \
+ .min_uV = 500000, \
+ .max_uV = 1770000, \
+ .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
+ REGULATOR_MODE_STANDBY), \
+ .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
+ REGULATOR_CHANGE_STATUS | \
+ REGULATOR_CHANGE_VOLTAGE), \
+ .always_on = 1, \
+ .boot_on = 1, \
+ .apply_uV = 0, \
+ }, \
+ .num_consumer_supplies = ARRAY_SIZE(tps6236x_dcdc_supply), \
+ .consumer_supplies = tps6236x_dcdc_supply, \
+ }, \
+ .en_discharge = true, \
+ .vsel0_gpio = -1, \
+ .vsel1_gpio = -1, \
+ .vsel0_def_state = 1, \
+ .vsel1_def_state = 1, \
+};
+
+static struct i2c_board_info __initdata tps6236x_boardinfo[] = {
+ {
+ I2C_BOARD_INFO("tps62360", 0x60),
+ .platform_data = &tps6236x_pdata,
+ },
+};
+
+/* Macro for defining fixed regulator sub device data */
+#define FIXED_SUPPLY(_name) "fixed_reg_"#_name
+#define FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, \
+ _boot_on, _gpio_nr, _active_high, _boot_state, \
+ _millivolts, _od_state) \
+ static struct regulator_init_data ri_data_##_var = \
+ { \
+ .supply_regulator = _in_supply, \
+ .num_consumer_supplies = \
+ ARRAY_SIZE(fixed_reg_##_name##_supply), \
+ .consumer_supplies = fixed_reg_##_name##_supply, \
+ .constraints = { \
+ .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
+ REGULATOR_MODE_STANDBY), \
+ .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
+ REGULATOR_CHANGE_STATUS | \
+ REGULATOR_CHANGE_VOLTAGE), \
+ .always_on = _always_on, \
+ .boot_on = _boot_on, \
+ }, \
+ }; \
+ static struct fixed_voltage_config fixed_reg_##_var##_pdata = \
+ { \
+ .supply_name = FIXED_SUPPLY(_name), \
+ .microvolts = _millivolts * 1000, \
+ .gpio = _gpio_nr, \
+ .enable_high = _active_high, \
+ .enabled_at_boot = _boot_state, \
+ .init_data = &ri_data_##_var, \
+ .gpio_is_open_drain = _od_state, \
+ }; \
+ static struct platform_device fixed_reg_##_var##_dev = { \
+ .name = "reg-fixed-voltage", \
+ .id = _id, \
+ .dev = { \
+ .platform_data = &fixed_reg_##_var##_pdata, \
+ }, \
+ }
+
+#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \
+ _gpio_nr, _active_high, _boot_state, _millivolts) \
+ FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, _boot_on, \
+ _gpio_nr, _active_high, _boot_state, _millivolts, false)
+
+#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev)
+
+/* PMU GP6: EN_VDD_HDMI switching via FET: +V1.8_AVDD_HDMI_PLL and +V3.3_AVDD_HDMI */
+static struct regulator_consumer_supply fixed_reg_en_hdmi_supply[] = {
+ REGULATOR_SUPPLY("avdd_hdmi", NULL),
+ REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
+// REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL),
+// REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
+};
+
+FIXED_REG(2, en_hdmi, en_hdmi, NULL, 0, 0, TPS6591X_GPIO_6, true, 0, 1800);
+
+/* Gpio switch regulator platform data */
+static struct platform_device *fixed_reg_devs_colibri_t30[] = {
+ ADD_FIXED_REG(en_hdmi),
+};
+
+int __init colibri_t30_regulator_init(void)
+{
+ void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+ u32 pmc_ctrl;
+
+ /* configure the power management controller to trigger PMU
+ * interrupts when low */
+
+ pmc_ctrl = readl(pmc + PMC_CTRL);
+ writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+
+ /* The regulator details have complete constraints */
+ regulator_has_full_constraints();
+
+ tps_platform.num_subdevs =
+ ARRAY_SIZE(colibri_t30_tps_devs);
+ tps_platform.subdevs = colibri_t30_tps_devs;
+
+ i2c_register_board_info(4, colibri_t30_regulators, 1);
+
+ /* Register the TPS6236x. */
+ pr_info("Registering the device TPS62360\n");
+ i2c_register_board_info(4, tps6236x_boardinfo, 1);
+
+ return 0;
+}
+
+int __init colibri_t20_fixed_regulator_init(void)
+{
+ return platform_add_devices(fixed_reg_devs_colibri_t30, ARRAY_SIZE(fixed_reg_devs_colibri_t30));
+}
+subsys_initcall_sync(colibri_t20_fixed_regulator_init);
+
+static void colibri_t30_board_suspend(int lp_state, enum suspend_stage stg)
+{
+ if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
+ tegra_console_uart_suspend();
+}
+
+static void colibri_t30_board_resume(int lp_state, enum resume_stage stg)
+{
+ if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
+ tegra_console_uart_resume();
+}
+
+static struct tegra_suspend_platform_data colibri_t30_suspend_data = {
+ .cpu_timer = 2000,
+ .cpu_off_timer = 200,
+ .suspend_mode = TEGRA_SUSPEND_LP0,
+ .core_timer = 0x7e7e,
+ .core_off_timer = 0,
+ .corereq_high = true,
+ .sysclkreq_high = true,
+ .cpu_lp2_min_residency = 2000,
+ .board_suspend = colibri_t30_board_suspend,
+ .board_resume = colibri_t30_board_resume,
+};
+
+int __init colibri_t30_suspend_init(void)
+{
+ /* Make core_pwr_req to high */
+ colibri_t30_suspend_data.corereq_high = true;
+
+ /* CORE_PWR_REQ to be high required to enable the dc-dc converter tps62361x */
+ colibri_t30_suspend_data.corereq_high = true;
+
+//required?
+ colibri_t30_suspend_data.cpu_timer = 5000;
+ colibri_t30_suspend_data.cpu_off_timer = 5000;
+
+ tegra_init_suspend(&colibri_t30_suspend_data);
+ return 0;
+}
+
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+int __init colibri_t30_edp_init(void)
+{
+ unsigned int regulator_mA;
+
+ regulator_mA = get_maximum_cpu_current_supported();
+ if (!regulator_mA) {
+ regulator_mA = 6000; /* regular T30/s */
+ }
+ pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+
+ tegra_init_cpu_edp_limits(regulator_mA);
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-colibri_t30.c b/arch/arm/mach-tegra/board-colibri_t30.c
new file mode 100644
index 000000000000..22f345cf9943
--- /dev/null
+++ b/arch/arm/mach-tegra/board-colibri_t30.c
@@ -0,0 +1,837 @@
+/*
+ * arch/arm/mach-tegra/board-colibri_t30.c
+ *
+ * Copyright (c) 2012, Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <linux/clk.h>
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-tegra.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/kernel.h>
+#include <linux/memblock.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+#include <linux/spi-tegra.h>
+#include <linux/tegra_uart.h>
+
+#include <mach/clk.h>
+#include <mach/i2s.h>
+#include <mach/io.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/nand.h>
+#include <mach/pinmux.h>
+#include <mach/sdhci.h>
+#include <mach/tegra_asoc_pdata.h>
+#include <mach/tegra_fiq_debugger.h>
+#include <mach/thermal.h>
+#include <mach/usb_phy.h>
+
+#include "board-colibri_t30.h"
+#include "board.h"
+#include "clock.h"
+#include "devices.h"
+#include "fuse.h"
+#include "gpio-names.h"
+#include "pm.h"
+#include "wdt-recovery.h"
+
+#define ETHERNET_VBUS_GPIO TEGRA_GPIO_PDD2
+#define ETHERNET_RESET_GPIO TEGRA_GPIO_PDD0
+
+#if 0
+/* Audio */
+
+static struct tegra_audio_platform_data tegra_i2s_pdata = {
+ .i2s_master = true,
+ .dma_on = true, /* use dma by default */
+ .i2s_master_clk = 48000,
+ .dev_clk_rate = 12288000,
+ .mode = AUDIO_FRAME_FORMAT_I2S,
+ .fifo_fmt = AUDIO_FIFO_PACK_16,
+ .bit_size = AUDIO_BIT_SIZE_16,
+ .i2s_bus_width = 32,
+ .dsp_bus_width = 16,
+};
+
+static struct tegra_audio_platform_data tegra_spdif_pdata = {
+ .dma_on = true, /* use dma by default */
+ .dev_clk_rate = 6144000,
+ .mode = SPDIF_BIT_MODE_MODE16BIT,
+ .fifo_fmt = AUDIO_FIFO_PACK_16,
+};
+
+//somehow required
+struct wired_jack_conf audio_wr_jack_conf = {
+ .hp_det_n = TEGRA_GPIO_PW2,
+ .cdc_irq = TEGRA_GPIO_PW3,
+// .en_spkr = WM8903_GP3,
+ .spkr_amp_reg = "vdd_3v3_spk_amp"
+};
+
+struct tegra_das_platform_data tegra_das_pdata = {
+ .tegra_dap_port_info_table = {
+ /* I2S0 <--> NULL */
+ [0] = {
+ .dac_port = tegra_das_port_none,
+ .codec_type = tegra_audio_codec_type_none,
+ .device_property = {
+ .num_channels = 0,
+ .bits_per_sample = 0,
+ .rate = 0,
+ .master = 0,
+ .lrck_high_left = false,
+ .dac_dap_data_comm_format = 0,
+ },
+ },
+ /* I2S1 <--> NULL */
+ [1] = {
+ .dac_port = tegra_das_port_none,
+ .codec_type = tegra_audio_codec_type_none,
+ .device_property = {
+ .num_channels = 0,
+ .bits_per_sample = 0,
+ .rate = 0,
+ .master = 0,
+ .lrck_high_left = false,
+ .dac_dap_data_comm_format = 0,
+ },
+ },
+ /* DAP3/I2S2 <--> Hifi Codec */
+ [2] = {
+ .dac_port = tegra_das_port_i2s2,
+ .codec_type = tegra_audio_codec_type_hifi,
+ .device_property = {
+ .num_channels = 2,
+ .bits_per_sample = 16,
+ .rate = 48000,
+ .master = 0,
+ .lrck_high_left = false,
+ .dac_dap_data_comm_format =
+ dac_dap_data_format_i2s,
+ },
+ },
+ /* I2S3 <--> NULL */
+ [3] = {
+ .dac_port = tegra_das_port_none,
+ .codec_type = tegra_audio_codec_type_none,
+ .device_property = {
+ .num_channels = 0,
+ .bits_per_sample = 0,
+ .rate = 0,
+ .master = 0,
+ .lrck_high_left = false,
+ .dac_dap_data_comm_format = 0,
+ },
+ },
+ /* I2S4 <--> NULL */
+ [4] = {
+ .dac_port = tegra_das_port_none,
+ .codec_type = tegra_audio_codec_type_none,
+ .device_property = {
+ .num_channels = 0,
+ .bits_per_sample = 0,
+ .rate = 0,
+ .master = 0,
+ .lrck_high_left = false,
+ .dac_dap_data_comm_format = 0,
+ },
+ },
+ },
+};
+
+static void __init colibri_t30_audio_init(void)
+{
+ tegra_i2s_device2.dev.platform_data = &tegra_i2s_pdata;
+ platform_device_register(&tegra_i2s_device2);
+
+ tegra_spdif_device.dev.platform_data = &tegra_spdif_pdata;
+ platform_device_register(&tegra_spdif_device);
+}
+#endif
+
+/* Camera */
+static struct platform_device tegra_camera = {
+ .name = "tegra_camera",
+ .id = -1,
+};
+
+/* Clocks */
+static struct tegra_clk_init_table colibri_t30_clk_init_table[] __initdata = {
+ /* name parent rate enabled */
+ { "audio1", "i2s1_sync", 0, false},
+ { "audio3", "i2s3_sync", 0, false},
+ { "blink", "clk_32k", 32768, true},
+ { "d_audio", "clk_m", 12000000, false},
+//{ "d_audio", "pll_a_out0", 12288000, false},
+ { "dam0", "clk_m", 12000000, false},
+ { "dam1", "clk_m", 12000000, false},
+ { "dam2", "clk_m", 12000000, false},
+ { "hda", "pll_p", 108000000, false},
+ { "hda2codec_2x","pll_p", 48000000, false},
+ { "i2c1", "pll_p", 3200000, false},
+ { "i2c2", "pll_p", 3200000, false},
+ { "i2c3", "pll_p", 3200000, false},
+ { "i2c4", "pll_p", 3200000, false},
+ { "i2c5", "pll_p", 3200000, false},
+ { "i2s0", "pll_a_out0", 0, false},
+ { "i2s1", "pll_a_out0", 0, false},
+ { "i2s3", "pll_a_out0", 0, false},
+// { "pll_a", NULL, 552960000, false},
+// { "pll_a_out0", NULL, 12288000, false},
+ { "pll_m", NULL, 0, false},
+ { "pwm", "pll_p", 3187500, false},
+ { "spdif_out", "pll_a_out0", 0, false},
+ { "vi", "pll_p", 0, false},
+ { "vi_sensor", "pll_p", 150000000, false},
+ { NULL, NULL, 0, 0},
+};
+
+/* I2C */
+
+/* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier board) */
+static struct i2c_board_info colibri_t30_i2c_bus1_board_info[] __initdata = {
+ {
+ /* M41T0M6 real time clock on Iris carrier board */
+ I2C_BOARD_INFO("rtc-ds1307", 0x68),
+ .type = "m41t00",
+ },
+};
+
+static struct tegra_i2c_platform_data colibri_t30_i2c1_platform_data = {
+ .adapter_nr = 0,
+ .bus_count = 1,
+ .bus_clk_rate = { 100000, 0 },
+ .scl_gpio = {TEGRA_GPIO_PC4, 0},
+ .sda_gpio = {TEGRA_GPIO_PC5, 0},
+ .arb_recovery = arb_lost_recovery,
+};
+
+/* HDMI_DDC */
+static struct tegra_i2c_platform_data colibri_t30_i2c4_platform_data = {
+ .adapter_nr = 3,
+ .bus_count = 1,
+ .bus_clk_rate = { 10000, 0 },
+// .bus_clk_rate = { 100000, 0 },
+ .scl_gpio = {TEGRA_GPIO_PV4, 0},
+ .sda_gpio = {TEGRA_GPIO_PV5, 0},
+ .arb_recovery = arb_lost_recovery,
+};
+
+/* PWR_I2C */
+
+/* STMPE811 touch screen controller */
+static struct stmpe_ts_platform_data stmpe811_ts_data = {
+ .sample_time = 4, /* ADC converstion time: 80 clocks */
+ .mod_12b = 1, /* 12-bit ADC */
+ .ref_sel = 0, /* internal ADC reference */
+ .adc_freq = 1, /* 3.25 MHz ADC clock speed */
+ .ave_ctrl = 2, /* 4 sample average control */
+// .ave_ctrl = 3, /* 8 sample average control */
+ .touch_det_delay = 3, /* 500 us touch detect interrupt delay */
+ .settling = 2, /* 500 us panel driver settling time */
+// .settling = 3, /* 1 ms panel driver settling time */
+ .fraction_z = 7, /* 7 length fractional part in z */
+ .i_drive = 0, /* 20 mA typical 35 mA max touchscreen drivers current limit value */
+// .i_drive = 1, /* 50 mA typical 80 mA max touchscreen drivers current limit value */
+};
+
+static struct stmpe_platform_data stmpe811_data = {
+ .id = 1,
+ .blocks = STMPE_BLOCK_TOUCHSCREEN,
+ .irq_base = STMPE811_IRQ_BASE,
+ .irq_trigger = IRQF_TRIGGER_FALLING,
+ .ts = &stmpe811_ts_data,
+};
+
+static struct i2c_board_info colibri_t30_i2c_bus5_board_info[] __initdata = {
+ {
+ /* SGTL5000 audio codec */
+ I2C_BOARD_INFO("sgtl5000", 0x0a),
+ },
+ {
+ /* STMPE811 touch screen controller */
+ I2C_BOARD_INFO("stmpe", 0x41),
+ .type = "stmpe811",
+ .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PV0),
+ .platform_data = &stmpe811_data,
+ .flags = I2C_CLIENT_WAKE,
+ },
+ {
+ /* LM95245 temperature sensor */
+ I2C_BOARD_INFO("lm95245", 0x4c),
+ },
+};
+
+static struct tegra_i2c_platform_data colibri_t30_i2c5_platform_data = {
+ .adapter_nr = 4,
+ .bus_count = 1,
+// .bus_clk_rate = { 100000, 0 },
+ .bus_clk_rate = { 400000, 0 },
+ .scl_gpio = {TEGRA_GPIO_PZ6, 0},
+ .sda_gpio = {TEGRA_GPIO_PZ7, 0},
+ .arb_recovery = arb_lost_recovery,
+};
+
+static void __init colibri_t30_i2c_init(void)
+{
+ tegra_i2c_device1.dev.platform_data = &colibri_t30_i2c1_platform_data;
+ tegra_i2c_device4.dev.platform_data = &colibri_t30_i2c4_platform_data;
+ tegra_i2c_device5.dev.platform_data = &colibri_t30_i2c5_platform_data;
+
+ i2c_register_board_info(0, colibri_t30_i2c_bus1_board_info, ARRAY_SIZE(colibri_t30_i2c_bus1_board_info));
+
+ /* setting audio codec on i2c_4 */
+ i2c_register_board_info(4, colibri_t30_i2c_bus5_board_info, ARRAY_SIZE(colibri_t30_i2c_bus5_board_info));
+
+ platform_device_register(&tegra_i2c_device5);
+ platform_device_register(&tegra_i2c_device4);
+ platform_device_register(&tegra_i2c_device1);
+}
+
+/* MMC/SD */
+
+static struct tegra_sdhci_platform_data colibri_t30_emmc_platform_data = {
+ .cd_gpio = -1,
+//.ddr_clk_limit = 41000000,
+ .ddr_clk_limit = 52000000,
+ .is_8bit = 1,
+ .mmc_data = {
+ .built_in = 1,
+ },
+ .power_gpio = -1,
+//.tap_delay = 6,
+ .tap_delay = 0x0f,
+ .wp_gpio = -1,
+};
+
+static struct tegra_sdhci_platform_data colibri_t30_sdcard_platform_data = {
+ .cd_gpio = TEGRA_GPIO_PU6, /* MM_CD */
+//.ddr_clk_limit = 41000000,
+ .ddr_clk_limit = 52000000,
+ .power_gpio = -1,
+//.tap_delay = 6,
+ .tap_delay = 0x0f,
+ .wp_gpio = -1,
+};
+
+static void __init colibri_t30_sdhci_init(void)
+{
+ /* register eMMC first */
+ tegra_sdhci_device4.dev.platform_data =
+#ifdef COLIBRI_T30_SDMMC4B
+ &colibri_t30_sdcard_platform_data;
+#else
+ &colibri_t30_emmc_platform_data;
+#endif
+ platform_device_register(&tegra_sdhci_device4);
+
+#ifndef COLIBRI_T30_SDMMC4B
+ tegra_sdhci_device2.dev.platform_data =
+ &colibri_t30_sdcard_platform_data;
+ platform_device_register(&tegra_sdhci_device2);
+#endif
+}
+
+#if 0
+/* NAND */
+
+#if defined(CONFIG_MTD_NAND_TEGRA)
+static struct resource nand_resources[] = {
+ [0] = {
+ .start = INT_NANDFLASH,
+ .end = INT_NANDFLASH,
+ .flags = IORESOURCE_IRQ
+ },
+ [1] = {
+ .start = TEGRA_NAND_BASE,
+ .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct tegra_nand_chip_parms nand_chip_parms[] = {
+ /* Micron MT29F16G08CBACA */
+ [0] = {
+ .vendor_id = 0x2c,
+ .device_id = 0x48,
+ .read_id_fourth_byte = 0x4a,
+ .capacity = 2048,
+ .timing = {
+ /* mode 4 */
+ .trp = 12,
+ .trh = 10, /* tREH */
+ .twp = 12,
+ .twh = 10,
+ .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */
+ .twhr = 60,
+ .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */
+ .twb = 100,
+ .trp_resp = 12, /* tRP */
+ .tadl = 70,
+ },
+ },
+};
+
+static struct tegra_nand_platform nand_data = {
+ .max_chips = 8,
+ .chip_parms = nand_chip_parms,
+ .nr_chip_parms = ARRAY_SIZE(nand_chip_parms),
+};
+
+static struct platform_device tegra_nand_device = {
+ .name = "tegra_nand",
+ .id = -1,
+ .resource = nand_resources,
+ .num_resources = ARRAY_SIZE(nand_resources),
+ .dev = {
+ .platform_data = &nand_data,
+ },
+};
+
+static void __init colibri_t30_nand_init(void)
+{
+ /* eMMC vs. NAND flash detection */
+ if (!gpio_get_value(TEGRA_GPIO_PC7)) {
+ pr_info("Detected NAND flash variant, registering controller driver.\n");
+ platform_device_register(&tegra_nand_device);
+ }
+ tegra_gpio_disable(TEGRA_GPIO_PC7);
+}
+#else
+static inline void colibri_t30_nand_init(void) {}
+#endif
+#endif
+
+/* RTC */
+
+#if defined(CONFIG_RTC_DRV_TEGRA)
+static struct resource tegra_rtc_resources[] = {
+ [0] = {
+ .start = TEGRA_RTC_BASE,
+ .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_RTC,
+ .end = INT_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tegra_rtc_device = {
+ .name = "tegra_rtc",
+ .id = -1,
+ .resource = tegra_rtc_resources,
+ .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+#endif
+
+/* SPI */
+//TBR
+static struct platform_device *colibri_t30_spi_devices[] __initdata = {
+ &tegra_spi_device4,
+};
+
+static struct spi_clk_parent spi_parent_clk[] = {
+ [0] = {.name = "pll_p"},
+ [1] = {.name = "pll_m"},
+ [2] = {.name = "clk_m"},
+};
+
+static struct tegra_spi_platform_data colibri_t30_spi_pdata = {
+ .is_dma_based = true,
+ .max_dma_buffer = (16 * 1024),
+ .is_clkon_always = false,
+ .max_rate = 100000000,
+};
+
+static void __init colibri_t30_spi_init(void)
+{
+ int i;
+ struct clk *c;
+
+ for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
+ c = tegra_get_clock_by_name(spi_parent_clk[i].name);
+ if (IS_ERR_OR_NULL(c)) {
+ pr_err("Not able to get the clock for %s\n",
+ spi_parent_clk[i].name);
+ continue;
+ }
+ spi_parent_clk[i].parent_clk = c;
+ spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+ }
+ colibri_t30_spi_pdata.parent_clk_list = spi_parent_clk;
+ colibri_t30_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
+ tegra_spi_device4.dev.platform_data = &colibri_t30_spi_pdata;
+ platform_add_devices(colibri_t30_spi_devices,
+ ARRAY_SIZE(colibri_t30_spi_devices));
+}
+
+/* UART */
+
+static struct platform_device *colibri_t30_uart_devices[] __initdata = {
+ &tegra_uarta_device, /* FF */
+ &tegra_uartb_device, /* STD */
+ &tegra_uartd_device, /* BT */
+};
+
+static struct uart_clk_parent uart_parent_clk[] = {
+ [0] = {.name = "clk_m"},
+ [1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+ [2] = {.name = "pll_m"},
+#endif
+};
+
+//can't be initdata
+static struct tegra_uart_platform_data colibri_t30_uart_pdata;
+
+static void __init uart_debug_init(void)
+{
+ int debug_port_id;
+
+ debug_port_id = get_tegra_uart_debug_port_id();
+ if (debug_port_id < 0) {
+ debug_port_id = 0;
+ }
+
+ switch (debug_port_id) {
+ case 0:
+ /* UARTA is the debug port. */
+ pr_info("Selecting UARTA as the debug console\n");
+ colibri_t30_uart_devices[0] = &debug_uarta_device;
+ debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+ debug_uart_port_base = ((struct plat_serial8250_port *)(
+ debug_uarta_device.dev.platform_data))->mapbase;
+ break;
+
+ case 1:
+ /* UARTB is the debug port. */
+ pr_info("Selecting UARTB as the debug console\n");
+ colibri_t30_uart_devices[1] = &debug_uartb_device;
+ debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
+ debug_uart_port_base = ((struct plat_serial8250_port *)(
+ debug_uartb_device.dev.platform_data))->mapbase;
+ break;
+
+ case 3:
+ /* UARTD is the debug port. */
+ pr_info("Selecting UARTD as the debug console\n");
+ colibri_t30_uart_devices[2] = &debug_uartd_device;
+ debug_uart_clk = clk_get_sys("serial8250.0", "uartd");
+ debug_uart_port_base = ((struct plat_serial8250_port *)(
+ debug_uartd_device.dev.platform_data))->mapbase;
+ break;
+
+ default:
+ pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
+ colibri_t30_uart_devices[0] = &debug_uarta_device;
+ debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+ debug_uart_port_base = ((struct plat_serial8250_port *)(
+ debug_uarta_device.dev.platform_data))->mapbase;
+ break;
+ }
+ return;
+}
+
+static void __init colibri_t30_uart_init(void)
+{
+ struct clk *c;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+ c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+ if (IS_ERR_OR_NULL(c)) {
+ pr_err("Not able to get the clock for %s\n",
+ uart_parent_clk[i].name);
+ continue;
+ }
+ uart_parent_clk[i].parent_clk = c;
+ uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+ }
+ colibri_t30_uart_pdata.parent_clk_list = uart_parent_clk;
+ colibri_t30_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+ tegra_uarta_device.dev.platform_data = &colibri_t30_uart_pdata;
+ tegra_uartb_device.dev.platform_data = &colibri_t30_uart_pdata;
+ tegra_uartd_device.dev.platform_data = &colibri_t30_uart_pdata;
+
+ /* Register low speed only if it is selected */
+ if (!is_tegra_debug_uartport_hs()) {
+ uart_debug_init();
+ /* Clock enable for the debug channel */
+ if (!IS_ERR_OR_NULL(debug_uart_clk)) {
+ pr_info("The debug console clock name is %s\n",
+ debug_uart_clk->name);
+ c = tegra_get_clock_by_name("pll_p");
+ if (IS_ERR_OR_NULL(c))
+ pr_err("Not getting the parent clock pll_p\n");
+ else
+ clk_set_parent(debug_uart_clk, c);
+
+ clk_enable(debug_uart_clk);
+ clk_set_rate(debug_uart_clk, clk_get_rate(c));
+ } else {
+ pr_err("Not getting the clock %s for debug console\n",
+ debug_uart_clk->name);
+ }
+ }
+
+ platform_add_devices(colibri_t30_uart_devices,
+ ARRAY_SIZE(colibri_t30_uart_devices));
+}
+
+/* USB */
+
+#if defined(CONFIG_USB_SUPPORT)
+#if 0
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .vbus_reg = "vdd_vbus_micro_usb",
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+#endif
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = TEGRA_GPIO_PW2, /* USBH_PEN */
+ .vbus_gpio_inverted = 1,
+// .vbus_reg = NULL,
+// .vbus_reg = "vdd_vbus_typea_usb",
+ .hot_plug = true,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+#if 0
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+ .ehci_device = &tegra_ehci1_device,
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+#endif
+
+static void colibri_t30_usb_init(void)
+{
+#if 0
+ /* OTG should be the first to be registered */
+ tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+ platform_device_register(&tegra_otg_device);
+
+ /* setup the udc platform data */
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+#endif
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
+ platform_device_register(&tegra_ehci2_device);
+
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
+ platform_device_register(&tegra_ehci3_device);
+}
+#else /* CONFIG_USB_SUPPORT */
+static inline void colibri_t30_usb_init(void) { }
+#endif /* CONFIG_USB_SUPPORT */
+
+static struct platform_device *colibri_t30_devices[] __initdata = {
+ &tegra_pmu_device,
+#if defined(CONFIG_RTC_DRV_TEGRA)
+ &tegra_rtc_device,
+#endif
+ &tegra_udc_device,
+#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
+ &tegra_smmu_device,
+#endif
+ &tegra_wdt0_device,
+ &tegra_wdt1_device,
+ &tegra_wdt2_device,
+#if defined(CONFIG_TEGRA_AVP)
+ &tegra_avp_device,
+#endif
+ &tegra_camera,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
+ &tegra_se_device,
+#endif
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+ &tegra_aes_device,
+#endif
+#if 0
+ &tegra_ahub_device,
+ &tegra_dam_device0,
+ &tegra_dam_device1,
+ &tegra_dam_device2,
+ &tegra_i2s_device0,
+ &tegra_i2s_device1,
+ &tegra_i2s_device3,
+ &tegra_spdif_device,
+ &spdif_dit_device,
+ &tegra_pcm_device,
+#endif
+ &tegra_cec_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+ &tegra_aes_device,
+#endif
+};
+
+static void __init colibri_t30_init(void)
+{
+#if 0
+ tegra_thermal_init(&thermal_data,
+ throttle_list,
+ ARRAY_SIZE(throttle_list));
+#endif
+ tegra_clk_init_from_table(colibri_t30_clk_init_table);
+ colibri_t30_pinmux_init();
+ colibri_t30_i2c_init();
+ colibri_t30_spi_init();
+ colibri_t30_usb_init();
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+ colibri_t30_edp_init();
+#endif
+ colibri_t30_uart_init();
+ platform_add_devices(colibri_t30_devices, ARRAY_SIZE(colibri_t30_devices));
+ tegra_ram_console_debug_init();
+ colibri_t30_sdhci_init();
+ colibri_t30_regulator_init();
+ colibri_t30_suspend_init();
+ colibri_t30_panel_init();
+// colibri_t30_sensors_init();
+ colibri_t30_pins_state_init();
+ colibri_t30_emc_init();
+// colibri_t30_nand_init();
+ tegra_release_bootloader_fb();
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+ tegra_wdt_recovery_init();
+#endif
+ tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
+}
+
+static void __init colibri_t30_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+ /* support 1920X1200 with 24bpp */
+// tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
+ /* Support 1920X1080 32bpp,double buffered on HDMI*/
+ tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
+#else
+ tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
+#endif
+ tegra_ram_console_debug_reserve(SZ_1M);
+}
+
+MACHINE_START(COLIBRI_T30, "Toradex Colibri T30")
+ .boot_params = 0x80000100,
+ .init_early = tegra_init_early,
+ .init_irq = tegra_init_irq,
+ .init_machine = colibri_t30_init,
+ .map_io = tegra_map_common_io,
+ .reserve = colibri_t30_reserve,
+ .timer = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-colibri_t30.h b/arch/arm/mach-tegra/board-colibri_t30.h
new file mode 100644
index 000000000000..b67082a5b4cf
--- /dev/null
+++ b/arch/arm/mach-tegra/board-colibri_t30.h
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/mach-tegra/board-colibri_t30.h
+ *
+ * Copyright (c) 2012 Toradex, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_COLIBRI_T30_H
+#define _MACH_TEGRA_BOARD_COLIBRI_T30_H
+
+#include <linux/mfd/tps6591x.h>
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+/* External peripheral act as gpio */
+/* TPS6591x GPIOs */
+#define TPS6591X_GPIO_BASE TEGRA_NR_GPIOS
+#define TPS6591X_GPIO_0 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP0)
+#define TPS6591X_GPIO_1 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP1)
+#define TPS6591X_GPIO_2 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP2)
+#define TPS6591X_GPIO_3 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP3)
+#define TPS6591X_GPIO_4 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP4)
+#define TPS6591X_GPIO_5 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP5)
+#define TPS6591X_GPIO_6 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP6)
+#define TPS6591X_GPIO_7 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP7)
+#define TPS6591X_GPIO_8 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP8)
+#define TPS6591X_GPIO_END (TPS6591X_GPIO_BASE + TPS6591X_GPIO_NR)
+
+#define AC_PRESENT_GPIO TPS6591X_GPIO_4
+
+/*****************Interrupt tables ******************/
+/* External peripheral act as interrupt controller */
+/* TPS6591x IRQs */
+#define TPS6591X_IRQ_BASE TEGRA_NR_IRQS
+#define TPS6591X_IRQ_END (TPS6591X_IRQ_BASE + 18)
+
+#define AC_PRESENT_INT (TPS6591X_INT_GPIO4 + TPS6591X_IRQ_BASE)
+
+/* STMPE811 IRQs */
+#define STMPE811_IRQ_BASE TPS6591X_IRQ_END
+#define STMPE811_IRQ_END (STMPE811_IRQ_BASE + 22)
+
+//#define COLIBRI_T30_SDMMC4B /* SD-card on SDMMC4B rather than SDMMC2 */
+//#define COLIBRI_T30_VI
+
+int colibri_t30_regulator_init(void);
+int colibri_t30_suspend_init(void);
+int colibri_t30_pinmux_init(void);
+int colibri_t30_panel_init(void);
+int colibri_t30_sensors_init(void);
+int colibri_t30_gpio_switch_regulator_init(void);
+int colibri_t30_pins_state_init(void);
+int colibri_t30_emc_init(void);
+int colibri_t30_power_off_init(void);
+int colibri_t30_edp_init(void);
+
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-26 19:01:30 +0000