diff options
| author | naveenk <naveenk@nvidia.com> | 2011-08-12 19:46:35 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:16 -0800 |
| commit | e076713aeaff1b539d10ea6f80070c4a86f636ed (patch) | |
| tree | 6fe9edb1938e15bfb72cec2bb31729ac69eeb357 /arch/arm/mach-tegra | |
| parent | 9cdd7bcff7e5d9a279aeb69c2410805581f6015d (diff) | |
ARM: Tegra: Cardhu: Setting sdmmc drive strengths
configuring sdmmc drive strengths as suggested
by HW team based on Characterization results
Bug 799568
Original-Change-Id: Id30505659aefb9c63a24f8baa8296a62723710b4
Reviewed-on: http://git-master/r/46949
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R4d0b228317fd12c185b735ed248818f5217d9ed4
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/board-cardhu-pinmux.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/pinmux.h | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c index fcf6d77c07c5..3ecb649f7be4 100644 --- a/arch/arm/mach-tegra/board-cardhu-pinmux.c +++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c @@ -87,7 +87,7 @@ static __initdata struct tegra_drive_pingroup_config cardhu_drive_pinmux[] = { SET_DRIVE(UART3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), /* SDMMC1 */ - SET_DRIVE(SDIO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + SET_DRIVE(SDIO1, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST), /* SDMMC3 */ SET_DRIVE(SDIO3, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index 0b9a8c69ceaa..a92f6c602653 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h @@ -254,6 +254,21 @@ enum tegra_pull_strength { TEGRA_PULL_29, TEGRA_PULL_30, TEGRA_PULL_31, + TEGRA_PULL_32, + TEGRA_PULL_33, + TEGRA_PULL_34, + TEGRA_PULL_35, + TEGRA_PULL_36, + TEGRA_PULL_37, + TEGRA_PULL_38, + TEGRA_PULL_39, + TEGRA_PULL_40, + TEGRA_PULL_41, + TEGRA_PULL_42, + TEGRA_PULL_43, + TEGRA_PULL_44, + TEGRA_PULL_45, + TEGRA_PULL_46, TEGRA_MAX_PULL, }; |