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authorLinus Walleij <linus.walleij@stericsson.com>2010-06-23 07:59:48 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-07-09 14:46:47 +0100
commitd9e38040ccf9eb06b9b41c393c512ceb23f51a7f (patch)
treeca6103a3d1976832031e2c6561ce768432ce75ad /arch/arm/mach-ux500/clock.c
parent398aa66827155ef52bab58bebd24597d90968929 (diff)
ARM: 6184/2: ux500: use neutral PRCMU base
The MTU wallclock timing fix-up patch was hardwired to the DB8500 causing a regression. This makes it work on the DB5500 as well. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-ux500/clock.c')
-rw-r--r--arch/arm/mach-ux500/clock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index fe84b9021c7a..0a1318fc8e2b 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -131,7 +131,7 @@ EXPORT_SYMBOL(clk_disable);
*/
static unsigned long clk_mtu_get_rate(struct clk *clk)
{
- void __iomem *addr = __io_address(U8500_PRCMU_BASE)
+ void __iomem *addr = __io_address(UX500_PRCMU_BASE)
+ PRCM_TCR;
u32 tcr = readl(addr);
int mtu = (int) clk->data;