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authorRabin Vincent <rabin.vincent@stericsson.com>2010-12-08 11:07:56 +0530
committerLinus Walleij <linus.walleij@stericsson.com>2010-12-08 13:25:41 +0100
commit22039b7cc54a636f80434e9b149fcdec148c4cb9 (patch)
tree42ded161697bc869237ef76672a9563186d9f5af /arch/arm/mach-ux500/include/mach
parent01afdd1353ca83904f430be4f6202d1a20912f4d (diff)
ux500: remove ambiguous irq macros
Remove the irq number macros which don't specify which SoC they're for. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Diffstat (limited to 'arch/arm/mach-ux500/include/mach')
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h44
1 files changed, 0 insertions, 44 deletions
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 693aa57de88d..880ae45bc235 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -21,50 +21,6 @@
/* Interrupt numbers generic for shared peripheral */
#define IRQ_MTU0 (IRQ_SHPI_START + 4)
-#define IRQ_SPI2 (IRQ_SHPI_START + 6)
-#define IRQ_SPI0 (IRQ_SHPI_START + 8)
-#define IRQ_UART0 (IRQ_SHPI_START + 11)
-#define IRQ_I2C3 (IRQ_SHPI_START + 12)
-#define IRQ_SSP0 (IRQ_SHPI_START + 14)
-#define IRQ_MTU1 (IRQ_SHPI_START + 17)
-#define IRQ_RTC_RTT (IRQ_SHPI_START + 18)
-#define IRQ_UART1 (IRQ_SHPI_START + 19)
-#define IRQ_I2C0 (IRQ_SHPI_START + 21)
-#define IRQ_I2C1 (IRQ_SHPI_START + 22)
-#define IRQ_USBOTG (IRQ_SHPI_START + 23)
-#define IRQ_DMA (IRQ_SHPI_START + 25)
-#define IRQ_UART2 (IRQ_SHPI_START + 26)
-#define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29)
-#define IRQ_MSP0 (IRQ_SHPI_START + 31)
-#define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
-#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
-#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
-#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
-#define IRQ_AB8500 (IRQ_SHPI_START + 40)
-#define IRQ_PRCMU (IRQ_SHPI_START + 47)
-#define IRQ_DISP (IRQ_SHPI_START + 48)
-#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
-#define IRQ_I2C4 (IRQ_SHPI_START + 51)
-#define IRQ_SSP1 (IRQ_SHPI_START + 52)
-#define IRQ_I2C2 (IRQ_SHPI_START + 55)
-#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
-#define IRQ_MSP1 (IRQ_SHPI_START + 62)
-#define IRQ_SPI1 (IRQ_SHPI_START + 96)
-#define IRQ_MSP2 (IRQ_SHPI_START + 98)
-#define IRQ_SDMMC4 (IRQ_SHPI_START + 99)
-#define IRQ_HSIRD0 (IRQ_SHPI_START + 104)
-#define IRQ_HSIRD1 (IRQ_SHPI_START + 105)
-#define IRQ_HSITD0 (IRQ_SHPI_START + 106)
-#define IRQ_HSITD1 (IRQ_SHPI_START + 107)
-#define IRQ_GPIO0 (IRQ_SHPI_START + 119)
-#define IRQ_GPIO1 (IRQ_SHPI_START + 120)
-#define IRQ_GPIO2 (IRQ_SHPI_START + 121)
-#define IRQ_GPIO3 (IRQ_SHPI_START + 122)
-#define IRQ_GPIO4 (IRQ_SHPI_START + 123)
-#define IRQ_GPIO5 (IRQ_SHPI_START + 124)
-#define IRQ_GPIO6 (IRQ_SHPI_START + 125)
-#define IRQ_GPIO7 (IRQ_SHPI_START + 126)
-#define IRQ_GPIO8 (IRQ_SHPI_START + 127)
/* There are 128 shared peripheral interrupts assigned to
* INTID[160:32]. The first 32 interrupts are reserved.