diff options
| author | Todd Poynor <toddpoynor@google.com> | 2011-02-15 11:48:42 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:41:40 -0800 |
| commit | 4ab864e98ea944e273cbfffcfcc1b258625a8a55 (patch) | |
| tree | 659a49c14b3006396dc90a07ace387b84b0473f8 /arch/arm/mm | |
| parent | 83adb17804d48ead8fc91a8ab7dda81db13b9444 (diff) | |
ARM: Cortex-A9: Enable dynamic clock gating
Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM. This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.
Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.
Original-Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Rebase-Id: R7ae4d4825e9171bca2471fe776ecf363e75b9ca6
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 848ae126b5f3..bfea95af079f 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -346,6 +346,16 @@ __v7_setup: 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number teq r0, r10 bne 3f + cmp r6, #0x10 @ power ctrl reg added r1p0 + mrcge p15, 0, r10, c15, c0, 0 @ read power control register + orrge r10, r10, #1 @ enable dynamic clock gating + mcrge p15, 0, r10, c15, c0, 0 @ write power control register +#ifdef CONFIG_ARM_ERRATA_720791 + teq r5, #0x00100000 @ only present in r1p* + mrceq p15, 0, r10, c15, c0, 2 @ read "chicken power ctrl" reg + orreq r10, r10, #0x30 @ disable core clk gate on + mcreq p15, 0, r10, c15, c0, 2 @ instr-side waits +#endif #ifdef CONFIG_ARM_ERRATA_742230 cmp r6, #0x22 @ only present up to r2p2 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register |