diff options
author | Sang-Hun Lee <sanlee@nvidia.com> | 2012-04-16 10:55:04 -0700 |
---|---|---|
committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-19 07:41:37 -0700 |
commit | d37014951a2e983935311582d72ad1fd48db6f5c (patch) | |
tree | eb7efed348af4a3fdcfe8c1e65f479f585258636 /arch/arm/mm | |
parent | 1402e0b6a6069de57972e63821fd60e9e9fcc170 (diff) |
Revert "ARM: pm: only use preallocated page table during resume"
This reverts commit 46d9f14943770c24603ef7cdfd8eb2dbcd3c1248.
Bug 967887
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Change-Id: Iee732d8137043240902201d7783d2c3fede98fbe
Reviewed-on: http://git-master/r/96794
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/proc-arm920.S | 17 | ||||
-rw-r--r-- | arch/arm/mm/proc-arm926.S | 17 | ||||
-rw-r--r-- | arch/arm/mm/proc-sa1100.S | 21 | ||||
-rw-r--r-- | arch/arm/mm/proc-v6.S | 31 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 51 | ||||
-rw-r--r-- | arch/arm/mm/proc-xsc3.S | 22 | ||||
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 21 |
7 files changed, 91 insertions, 89 deletions
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 88fb3d9e0640..035d57bf1b7a 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -379,26 +379,27 @@ ENTRY(cpu_arm920_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size -.equ cpu_arm920_suspend_size, 4 * 3 +.equ cpu_arm920_suspend_size, 4 * 4 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm920_do_suspend) - stmfd sp!, {r4 - r6, lr} + stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c1, c0, 0 @ Control register - stmia r0, {r4 - r6} - ldmfd sp!, {r4 - r6, pc} + mrc p15, 0, r6, c2, c0, 0 @ TTB address + mrc p15, 0, r7, c1, c0, 0 @ Control register + stmia r0, {r4 - r7} + ldmfd sp!, {r4 - r7, pc} ENDPROC(cpu_arm920_do_suspend) ENTRY(cpu_arm920_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches - ldmia r0, {r4 - r6} + ldmia r0, {r4 - r7} mcr p15, 0, r4, c13, c0, 0 @ PID mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r1, c2, c0, 0 @ TTB address - mov r0, r6 @ control register + mcr p15, 0, r6, c2, c0, 0 @ TTB address + mov r0, r7 @ control register b cpu_resume_mmu ENDPROC(cpu_arm920_do_resume) #endif diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 9f8fd91f918a..48add848b997 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -394,26 +394,27 @@ ENTRY(cpu_arm926_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm926_suspend_size -.equ cpu_arm926_suspend_size, 4 * 3 +.equ cpu_arm926_suspend_size, 4 * 4 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm926_do_suspend) - stmfd sp!, {r4 - r6, lr} + stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c1, c0, 0 @ Control register - stmia r0, {r4 - r6} - ldmfd sp!, {r4 - r6, pc} + mrc p15, 0, r6, c2, c0, 0 @ TTB address + mrc p15, 0, r7, c1, c0, 0 @ Control register + stmia r0, {r4 - r7} + ldmfd sp!, {r4 - r7, pc} ENDPROC(cpu_arm926_do_suspend) ENTRY(cpu_arm926_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches - ldmia r0, {r4 - r6} + ldmia r0, {r4 - r7} mcr p15, 0, r4, c13, c0, 0 @ PID mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r1, c2, c0, 0 @ TTB address - mov r0, r6 @ control register + mcr p15, 0, r6, c2, c0, 0 @ TTB address + mov r0, r7 @ control register b cpu_resume_mmu ENDPROC(cpu_arm926_do_resume) #endif diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 7d91545d089b..52f73fb47ac1 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -168,19 +168,20 @@ ENTRY(cpu_sa1100_set_pte_ext) mov pc, lr .globl cpu_sa1100_suspend_size -.equ cpu_sa1100_suspend_size, 4 * 3 +.equ cpu_sa1100_suspend_size, 4*4 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_sa1100_do_suspend) - stmfd sp!, {r4 - r6, lr} + stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c3, c0, 0 @ domain ID - mrc p15, 0, r5, c13, c0, 0 @ PID - mrc p15, 0, r6, c1, c0, 0 @ control reg - stmia r0, {r4 - r6} @ store cp regs - ldmfd sp!, {r4 - r6, pc} + mrc p15, 0, r5, c2, c0, 0 @ translation table base addr + mrc p15, 0, r6, c13, c0, 0 @ PID + mrc p15, 0, r7, c1, c0, 0 @ control reg + stmia r0, {r4 - r7} @ store cp regs + ldmfd sp!, {r4 - r7, pc} ENDPROC(cpu_sa1100_do_suspend) ENTRY(cpu_sa1100_do_resume) - ldmia r0, {r4 - r6} @ load cp regs + ldmia r0, {r4 - r7} @ load cp regs mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache @@ -188,9 +189,9 @@ ENTRY(cpu_sa1100_do_resume) mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB mcr p15, 0, r4, c3, c0, 0 @ domain ID - mcr p15, 0, r1, c2, c0, 0 @ translation table base addr - mcr p15, 0, r5, c13, c0, 0 @ PID - mov r0, r6 @ control register + mcr p15, 0, r5, c2, c0, 0 @ translation table base addr + mcr p15, 0, r6, c13, c0, 0 @ PID + mov r0, r7 @ control register b cpu_resume_mmu ENDPROC(cpu_sa1100_do_resume) #endif diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 2e27b467c6a6..414e3696bdf7 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -128,19 +128,20 @@ ENTRY(cpu_v6_set_pte_ext) /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ .globl cpu_v6_suspend_size -.equ cpu_v6_suspend_size, 4 * 7 +.equ cpu_v6_suspend_size, 4 * 8 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_v6_do_suspend) - stmfd sp!, {r4 - r10, lr} + stmfd sp!, {r4 - r11, lr} mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID mrc p15, 0, r5, c13, c0, 1 @ Context ID mrc p15, 0, r6, c3, c0, 0 @ Domain ID - mrc p15, 0, r7, c2, c0, 1 @ Translation table base 1 - mrc p15, 0, r8, c1, c0, 1 @ auxiliary control register - mrc p15, 0, r9, c1, c0, 2 @ co-processor access control - mrc p15, 0, r10, c1, c0, 0 @ control register - stmia r0, {r4 - r10} - ldmfd sp!, {r4- r10, pc} + mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 + mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 + mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register + mrc p15, 0, r10, c1, c0, 2 @ co-processor access control + mrc p15, 0, r11, c1, c0, 0 @ control register + stmia r0, {r4 - r11} + ldmfd sp!, {r4- r11, pc} ENDPROC(cpu_v6_do_suspend) ENTRY(cpu_v6_do_resume) @@ -149,19 +150,17 @@ ENTRY(cpu_v6_do_resume) mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache mcr p15, 0, ip, c7, c10, 4 @ drain write buffer - ldmia r0, {r4 - r10} + ldmia r0, {r4 - r11} mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID mcr p15, 0, r5, c13, c0, 1 @ Context ID mcr p15, 0, r6, c3, c0, 0 @ Domain ID - ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) - ALT_UP(orr r1, r1, #TTB_FLAGS_UP) - mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0 - mcr p15, 0, r7, c2, c0, 1 @ Translation table base 1 - mcr p15, 0, r8, c1, c0, 1 @ auxiliary control register - mcr p15, 0, r9, c1, c0, 2 @ co-processor access control + mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 + mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 + mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register + mcr p15, 0, r10, c1, c0, 2 @ co-processor access control mcr p15, 0, ip, c2, c0, 2 @ TTB control register mcr p15, 0, ip, c7, c5, 4 @ ISB - mov r0, r10 @ control register + mov r0, r11 @ control register b cpu_resume_mmu ENDPROC(cpu_v6_do_resume) #endif diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b29fa5c7a5ee..96385a7fee81 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -260,18 +260,19 @@ ENDPROC(cpu_v7_set_pte_ext) .equ cpu_v7_suspend_size, (4 * 10) + cpu_v7_debug_suspend_size #ifdef CONFIG_PM_SLEEP ENTRY(cpu_v7_do_suspend) - stmfd sp!, {r0, r3 - r10, lr} + stmfd sp!, {r0, r3 - r11, lr} mrc p15, 0, r3, c15, c0, 1 @ diag mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID mrc p15, 0, r5, c13, c0, 1 @ Context ID mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID stmia r0!, {r3 - r6} mrc p15, 0, r6, c3, c0, 0 @ Domain ID - mrc p15, 0, r7, c2, c0, 1 @ TTB 1 - mrc p15, 0, r8, c1, c0, 0 @ Control register - mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control - stmia r0!, {r6 - r10} + mrc p15, 0, r7, c2, c0, 0 @ TTB 0 + mrc p15, 0, r8, c2, c0, 1 @ TTB 1 + mrc p15, 0, r9, c1, c0, 0 @ Control register + mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control + stmia r0!, {r6 - r11} #ifdef CONFIG_ARM_SAVE_DEBUG_CONTEXT /* Save CP14 debug controller context */ @@ -296,7 +297,7 @@ ENTRY(cpu_v7_do_suspend) mrc p14, 0, r8, c0, c0, 0 @ read IDR mov r3, r8, lsr #24 - and r3, r3, #0xf @ r3 has the number of brkpt + and r3, r3, #0xf @ r3 has the number of brkpt rsb r3, r3, #0xf /* r3 = (15 - #of brkpt) ; @@ -323,7 +324,7 @@ ENTRY(cpu_v7_do_suspend) save_brkpt c1 save_brkpt c0 - mov r3, r8, lsr #28 @ r3 has the number of wpt + mov r3, r8, lsr #28 @ r3 has the number of wpt rsb r3, r3, #0xf /* r3 = (15 - #of wpt) ; @@ -350,7 +351,7 @@ ENTRY(cpu_v7_do_suspend) save_wpt c1 save_wpt c0 #endif - ldmfd sp!, {r0, r3 - r10, pc} + ldmfd sp!, {r0, r3 - r11, pc} ENDPROC(cpu_v7_do_suspend) ENTRY(cpu_v7_do_resume) @@ -364,17 +365,15 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID mcr p15, 0, r5, c13, c0, 1 @ Context ID mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID - ldmia r0!, {r6 - r10} + ldmia r0!, {r6 - r11} mcr p15, 0, r6, c3, c0, 0 @ Domain ID - ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) - ALT_UP(orr r1, r1, #TTB_FLAGS_UP) - mcr p15, 0, r1, c2, c0, 0 @ TTB 0 - mcr p15, 0, r7, c2, c0, 1 @ TTB 1 + mcr p15, 0, r7, c2, c0, 0 @ TTB 0 + mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register - teq r4, r9 @ Is it already set? - mcrne p15, 0, r9, c1, c0, 1 @ No, so write it - mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control + teq r4, r10 @ Is it already set? + mcrne p15, 0, r10, c1, c0, 1 @ No, so write it + mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR mcr p15, 0, r4, c10, c2, 0 @ write PRRR @@ -383,6 +382,7 @@ ENTRY(cpu_v7_do_resume) #ifdef CONFIG_ARM_SAVE_DEBUG_CONTEXT /* Restore CP14 debug controller context */ + ldmia r0!, {r2 - r5} mcr p14, 0, r3, c0, c6, 0 @ DBGWFAR mcr p14, 0, r4, c0, c7, 0 @ DBGVCR @@ -400,15 +400,14 @@ ENTRY(cpu_v7_do_resume) ldrne r4, [r0], #4 mcrne p14, 0, r4, c0, c0, 2 @ DBGDTRRXext - mrc p14, 0, r4, c0, c0, 0 @ read IDR - mov r3, r4, lsr #24 - and r3, r3, #0xf @ r3 has the number of brkpt + mrc p14, 0, r8, c0, c0, 0 @ read IDR + mov r3, r8, lsr #24 + and r3, r3, #0xf @ r3 has the number of brkpt rsb r3, r3, #0xf - /* - * r3 = (15 - # of wpt) ; - * switch offset = r3*12 - 4 = (r3*3 - 1)<<2 - */ + /* r3 = (15 - #of wpt) ; + switch offset = r3*12 - 4 = (r3*3 - 1)<<2 + */ add r3, r3, r3, lsl #1 sub r3, r3, #1 add pc, pc, r3, lsl #2 @@ -430,7 +429,7 @@ ENTRY(cpu_v7_do_resume) restore_brkpt c1 restore_brkpt c0 - mov r3, r4, lsr #28 @ r3 has the number of wpt + mov r3, r8, lsr #28 @ r3 has the number of wpt rsb r3, r3, #0xf /* r3 = (15 - #of wpt) ; @@ -463,7 +462,7 @@ start_restore_wpt: isb #endif dsb - mov r0, r8 @ Control Register + mov r0, r9 @ control register b cpu_resume_mmu ENDPROC(cpu_v7_do_resume) #endif diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 5ae0db4f44bd..f6607d315307 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -406,23 +406,24 @@ ENTRY(cpu_xsc3_set_pte_ext) .align .globl cpu_xsc3_suspend_size -.equ cpu_xsc3_suspend_size, 4 * 6 +.equ cpu_xsc3_suspend_size, 4 * 7 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_xsc3_do_suspend) - stmfd sp!, {r4 - r9, lr} + stmfd sp!, {r4 - r10, lr} mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode mrc p15, 0, r5, c15, c1, 0 @ CP access reg mrc p15, 0, r6, c13, c0, 0 @ PID mrc p15, 0, r7, c3, c0, 0 @ domain ID - mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg - mrc p15, 0, r9, c1, c0, 0 @ control reg + mrc p15, 0, r8, c2, c0, 0 @ translation table base addr + mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg + mrc p15, 0, r10, c1, c0, 0 @ control reg bic r4, r4, #2 @ clear frequency change bit - stmia r0, {r4 - r9} @ store cp regs - ldmia sp!, {r4 - r9, pc} + stmia r0, {r4 - r10} @ store cp regs + ldmia sp!, {r4 - r10, pc} ENDPROC(cpu_xsc3_do_suspend) ENTRY(cpu_xsc3_do_resume) - ldmia r0, {r4 - r9} @ load cp regs + ldmia r0, {r4 - r10} @ load cp regs mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer @@ -432,10 +433,9 @@ ENTRY(cpu_xsc3_do_resume) mcr p15, 0, r5, c15, c1, 0 @ CP access reg mcr p15, 0, r6, c13, c0, 0 @ PID mcr p15, 0, r7, c3, c0, 0 @ domain ID - orr r1, r1, #0x18 @ cache the page table in L2 - mcr p15, 0, r1, c2, c0, 0 @ translation table base addr - mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg - mov r0, r9 @ control register + mcr p15, 0, r8, c2, c0, 0 @ translation table base addr + mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg + mov r0, r10 @ control register b cpu_resume_mmu ENDPROC(cpu_xsc3_do_resume) #endif diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2b4152508d73..849fe463df57 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -520,23 +520,24 @@ ENTRY(cpu_xscale_set_pte_ext) .align .globl cpu_xscale_suspend_size -.equ cpu_xscale_suspend_size, 4 * 6 +.equ cpu_xscale_suspend_size, 4 * 7 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_xscale_do_suspend) - stmfd sp!, {r4 - r9, lr} + stmfd sp!, {r4 - r10, lr} mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode mrc p15, 0, r5, c15, c1, 0 @ CP access reg mrc p15, 0, r6, c13, c0, 0 @ PID mrc p15, 0, r7, c3, c0, 0 @ domain ID - mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg - mrc p15, 0, r9, c1, c0, 0 @ control reg + mrc p15, 0, r8, c2, c0, 0 @ translation table base addr + mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg + mrc p15, 0, r10, c1, c0, 0 @ control reg bic r4, r4, #2 @ clear frequency change bit - stmia r0, {r4 - r9} @ store cp regs - ldmfd sp!, {r4 - r9, pc} + stmia r0, {r4 - r10} @ store cp regs + ldmfd sp!, {r4 - r10, pc} ENDPROC(cpu_xscale_do_suspend) ENTRY(cpu_xscale_do_resume) - ldmia r0, {r4 - r9} @ load cp regs + ldmia r0, {r4 - r10} @ load cp regs mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB @@ -544,9 +545,9 @@ ENTRY(cpu_xscale_do_resume) mcr p15, 0, r5, c15, c1, 0 @ CP access reg mcr p15, 0, r6, c13, c0, 0 @ PID mcr p15, 0, r7, c3, c0, 0 @ domain ID - mcr p15, 0, r1, c2, c0, 0 @ translation table base addr - mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg - mov r0, r9 @ control register + mcr p15, 0, r8, c2, c0, 0 @ translation table base addr + mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg + mov r0, r10 @ control register b cpu_resume_mmu ENDPROC(cpu_xscale_do_resume) #endif |