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authorChris Johnson <cwj@nvidia.com>2011-11-18 16:14:07 -0800
committerVarun Wadekar <vwadekar@nvidia.com>2011-12-08 17:59:13 +0530
commit644d1fbf85ef31720cfefbe1f332767fe572e93a (patch)
treee79dae0187c03fef575bee42306e63ced5d668d7 /arch/arm/mm
parentd4808f8257f2868ac5dc29da2a266e975156c583 (diff)
arm: tegra: add Trusted Foundations hooks and driver
Add CONFIG_TRUSTED_FOUNDATIONS build option and calls to issue SMCs to the TL secure monitor (used when needing to update state not writable by non-secure code). Make security/tf_driver an optional part of the build, which is part of the TL framework to interact with secure services. Bug 883391 Change-Id: I9c6c14ff457fb3a0c612d558fe731a17c2480750 Signed-off-by: Chris Johnson <cwj@nvidia.com> Reviewed-on: http://git-master/r/65616 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-v7.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index d63d37f7e7dd..e666e4fe029c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -337,7 +337,9 @@ ENTRY(cpu_v7_do_resume)
mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
ldmia r0!, {r3 - r6}
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
mcr p15, 0, r3, c15, c0, 1 @ diag
+#endif
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
mcr p15, 0, r5, c13, c0, 1 @ Context ID
mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID
@@ -512,6 +514,7 @@ __v7_setup:
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
cmp r6, #0x10 @ power ctrl reg added r1p0
mrcge p15, 0, r10, c15, c0, 0 @ read power control register
orrge r10, r10, #1 @ enable dynamic clock gating
@@ -559,6 +562,7 @@ __v7_setup:
orrlt r10, r10, #1 << 20 @ set bit #20
mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
+#endif
3: mov r10, #0
#ifdef HARVARD_CACHE