diff options
| author | vdumpa <vdumpa@nvidia.com> | 2010-11-17 15:57:13 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:16 -0800 |
| commit | d89936edd10c1b3acae86d1fe699aa66c1398fb3 (patch) | |
| tree | d38f6c68a1f0e84df42ce0961bfe8b237365d0b6 /arch/arm/mm | |
| parent | 1f871e1b10d664cfac6d65fb09b8d35f7ddc839d (diff) | |
tegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributes
Change the cacheability attributes in the normal memory remap
register (NMRR) to inner write-back write-allocate/outer write-back
no-write-allocate to improve L2 cache performance.
Bug 728231
Bug 751146
Original-Change-Id: I992dd20b3cec3b0141ae114d5ae278122be0212d
Reviewed-on: http://git-master/r/11077
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/17475
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0de3100975c592fe4a18780c2b0eb2c5d12258d7
Rebase-Id: R430708cbf798ff30f5a5394a5235942e95bda2d4
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index bfea95af079f..3ffe4c5da864 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -213,7 +213,7 @@ ENDPROC(cpu_v7_set_pte_ext) * NOS = PRRR[24+n] = 1 - not outer shareable */ .equ PRRR, 0xff0a89a8 -.equ NMRR, 0x40e044e0 +.equ NMRR, 0xc0e044e0 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ .globl cpu_v7_suspend_size |