diff options
| author | Will Deacon <will.deacon@arm.com> | 2012-01-20 12:10:18 +0100 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-02-09 15:32:14 -0800 |
| commit | e2f193a470f7065100ad06950c71ca8688545a81 (patch) | |
| tree | ac4910292c0fa0aec748aa72b25ab29471d0d1b0 /arch/arm/mm | |
| parent | c8880d8b880e9d9b0f2dfdeda5dd65a0c75eb960 (diff) | |
ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards
commit 612539e81f655f6ac73c7af1da8701c1ee618aee upstream.
On v7, we use the same cache maintenance instructions for data lines
as for unified lines. This was not the case for v6, where HARVARD_CACHE
was defined to indicate the L1 cache topology.
This patch removes the erroneous compile-time check for HARVARD_CACHE in
proc-v7.S, ensuring that we perform I-side invalidation at boot.
Reported-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Catalin Marinas <Catalin.Marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I9a44ed525f4f702f9fac2965828608d9f1865633
Reviewed-on: http://git-master/r/79664
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index e666e4fe029c..9b1ee813994b 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -445,10 +445,6 @@ cpu_resume_l1_flags: * Initialise TLB, Caches, and MMU state ready to switch the MMU * on. Return in r0 the new CP15 C1 control register setting. * - * We automatically detect if we have a Harvard cache, and use the - * Harvard cache control instructions insead of the unified cache - * control instructions. - * * This should be able to cover all ARMv7 cores. * * It is assumed that: @@ -565,9 +561,7 @@ __v7_setup: #endif 3: mov r10, #0 -#ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -#endif dsb #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |