summaryrefslogtreecommitdiff
path: root/arch/arm/mm
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2015-06-03 13:10:16 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-07-25 15:28:11 +0100
commit4e1f8a6f1d978f033f1751e2887b3a69fab3f878 (patch)
treeda5a5e262f641d6e48db936295c79932901d7084 /arch/arm/mm
parentf81309067ff2d84788316c513a415f6bb8c9171f (diff)
ARM: add soc memory barrier extension
Add an extension to the heavy barrier code to allow a SoC specific memory barrier function to be provided. This is needed for platforms where the interconnect has weak ordering, and thus needs assistance to ensure that memory writes are properly visible in the correct order to other parts of the system. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/flush.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index ce6c2960d5ac..1ec8e7590fc6 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -22,12 +22,16 @@
#include "mm.h"
#ifdef CONFIG_ARM_HEAVY_MB
+void (*soc_mb)(void);
+
void arm_heavy_mb(void)
{
#ifdef CONFIG_OUTER_CACHE_SYNC
if (outer_cache.sync)
outer_cache.sync();
#endif
+ if (soc_mb)
+ soc_mb();
}
EXPORT_SYMBOL(arm_heavy_mb);
#endif