diff options
| author | Heechul Yun <hyun@nvidia.com> | 2011-06-30 15:40:43 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-08-22 15:25:05 -0700 |
| commit | 47f96cd19b00c6104b13328aba60529e45a53034 (patch) | |
| tree | 2c73940382b7db9b908ad6d379b4cb456c1af7cf /arch/arm/mm | |
| parent | 337ae1af765a59a9b5be1b98f6380b5f26b476b3 (diff) | |
arm: mm: Remove unnecessary cache flush on page table modification
Since MMU of Cortex-A9 read from L1-D not from memory, there's no
need to flush the cache line of the modified page table entry.
Original-Change-Id: Ie5e6a027f633ed6060b8d2a9fdcd6a5399736d55
Reviewed-on: http://git-master/r/39697
Reviewed-by: Heechul Yun <hyun@nvidia.com>
Tested-by: Heechul Yun <hyun@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index d78644caaf7d..3701d8f39e8e 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -168,7 +168,9 @@ ENTRY(cpu_v7_set_pte_ext) ARM( str r3, [r0, #2048]! ) THUMB( add r0, r0, #2048 ) THUMB( str r3, [r0] ) - mcr p15, 0, r0, c7, c10, 1 @ flush_pte + mrc p15, 0, r3, c0, c1, 7 @ read ID_MMFR3 + tst r3, #0xf << 20 @ check the coherent walk bits + mcreq p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext) |