diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-11-16 23:16:28 -0600 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-01-09 21:07:05 +0800 |
| commit | 8ef0b1cc9a9311719d632a3f26a14d64586b3fcd (patch) | |
| tree | de6aadd7556b4a4ccae7892957a9b2897acf36d5 /arch/arm/plat-mxc/dvfs_core.c | |
| parent | 193f0f2141ed9465e0de2ff549b9a152e52e5f93 (diff) | |
ENGR00162460:MX6-Revert "MX6-Disable PLL1 when CPU clk is below 400MHz."
This reverts commit 564e25cb10cd827ea3fa5cda2487fd978f08bbd7.
Sourcing ARM_CLK from PLL2_PFD_400M is causing issues when setting
the ARM_PODF. So for now source arm_clk from PLL1_SYS_MAIN only.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/dvfs_core.c')
| -rwxr-xr-x | arch/arm/plat-mxc/dvfs_core.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c index a8812d8ef612..f1a74ba503aa 100755 --- a/arch/arm/plat-mxc/dvfs_core.c +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -903,9 +903,6 @@ static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, dvfs_enable_show, dvfs_enable_store); static DEVICE_ATTR(show_regs, S_IRUGO, dvfs_regs_show, dvfs_regs_store); -static DEVICE_ATTR(down_threshold, 0644, downthreshold_show, - downthreshold_store); -static DEVICE_ATTR(down_count, 0644, downcount_show, downcount_store); /*! * This is the probe routine for the DVFS driver. @@ -996,20 +993,6 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) goto err3; } - err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_threshold.attr); - if (err) { - printk(KERN_ERR - "DVFS: Unable to register sysdev entry for DVFS"); - goto err3; - } - - err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr); - if (err) { - printk(KERN_ERR - "DVFS: Unable to register sysdev entry for DVFS"); - goto err3; - } - /* Set the current working point. */ cpu_op_tbl = get_cpu_op(&cpu_op_nr); old_op = 0; |