ENGR00174037-1 Add HSIC suspend/resume feature

MSL part

- For HSIC, not connect nor disconnect, then WKCN,
  WKDC must not be set during suspend
- For HSIC, must set bit 21 in host control registry
  after device connected to host controller
- USB PHY 480M clock output must turn on to avoid about
  10ms delay before sending out resume signal
- HW_ANA_MISC clkgate delay must be set to 2 or 3 to
  avoid 24M OSCI not stable issue

Signed-off-by: Tony LIU <junjie.liu@freescale.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
index b5bd8c31a4b2..bdb6b252b356 100755
--- a/arch/arm/plat-mxc/include/mach/arc_otg.h
+++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -248,6 +248,8 @@ extern void __iomem *imx_otg_base;
 #define PORTSC_PTW                      (1 << 28)       /* UTMI width */
 #define PORTSC_HSIC_MODE                (1 << 25)       /* Only for HSIC */
 #define PORTSC_PHCD                     (1 << 23)       /* Low Power Suspend */
+#define PORTSC_WKDC			(1 << 21)	/* wakeup on discnt*/
+#define PORTSC_WKCN			(1 << 20)	/* wakeup on connect*/
 #define PORTSC_PORT_POWER		(1 << 12)	/* port power */
 #define PORTSC_LS_MASK			(3 << 10)	/* Line State mask */
 #define PORTSC_LS_SE0			(0 << 10)	/* SE0     */