ENGR00153651-1 ESAI: Prepare MSL support for esai/cs42888 audio codec driver

1) Add machine specific code for esai/cs42888 driver support, including pad
    control, clk setting, i2c setting, etc.
2) Enable audio support in default config.

Signed-off-by: Lionel Xu <R63889@freescale.com>

1 files changed, 17 insertions, 14 deletions

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index 6a80467f499e..5fdceeba45fa 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -60,6 +60,9 @@ typedef enum iomux_config {
 		PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
 		PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
 
+#define MX6Q_ESAI_PAD_CTRL	(PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+		PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+
 #define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1				\
 		IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
 #define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0				\
@@ -5161,7 +5164,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_MDIO__ENET_MDIO		\
 		(_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_MDIO__ESAI1_SCKR		\
-		(_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3		\
 		(_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT		\
@@ -5176,7 +5179,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK		\
 		(_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
 #define  MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR		\
-		(_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4		\
 		(_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_REF_CLK__GPIO_1_23		\
@@ -5189,7 +5192,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_RX_ER__ENET_RX_ER		\
 		(_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR		\
-		(_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RX_ER__SPDIF_IN1		\
 		(_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT		\
@@ -5206,7 +5209,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN		\
 		(_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT		\
-		(_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK		\
 		(_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_CRS_DV__GPIO_1_25		\
@@ -5221,7 +5224,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_RXD1__ENET_RDATA_1		\
 		(_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RXD1__ESAI1_FST		\
-		(_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT		\
 		(_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RXD1__GPIO_1_26		\
@@ -5236,7 +5239,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_RXD0__ENET_RDATA_0		\
 		(_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RXD0__ESAI1_HCKT		\
-		(_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RXD0__SPDIF_OUT1		\
 		(_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RXD0__GPIO_1_27		\
@@ -5251,7 +5254,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_TX_EN__ENET_TX_EN		\
 		(_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2		\
-		(_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TX_EN__GPIO_1_28		\
 		(_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI		\
@@ -5264,7 +5267,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_TXD1__ENET_TDATA_1		\
 		(_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3		\
-		(_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN		\
 		(_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TXD1__GPIO_1_29		\
@@ -5279,7 +5282,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_TXD0__ENET_TDATA_0		\
 		(_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1		\
-		(_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TXD0__GPIO_1_30		\
 		(_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK		\
@@ -5292,7 +5295,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_MDC__ENET_MDC		\
 		(_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0		\
-		(_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN		\
 		(_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_MDC__GPIO_1_31		\
@@ -6186,7 +6189,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_CSI0_DAT8__KPP_COL_7		\
 		(_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT8__I2C1_SDA		\
-		(_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT8__GPIO_5_26		\
 		(_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47		\
@@ -6203,7 +6206,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_CSI0_DAT9__KPP_ROW_7		\
 		(_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT9__I2C1_SCL		\
-		(_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT9__GPIO_5_27		\
 		(_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48		\
@@ -6765,7 +6768,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_NANDF_CS2__IPU1_SISG_0		\
 		(_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_NANDF_CS2__ESAI1_TX0		\
-		(_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE		\
 		(_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_NANDF_CS2__CCM_CLKO2		\
@@ -6780,7 +6783,7 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_NANDF_CS3__IPU1_SISG_1		\
 		(_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_NANDF_CS3__ESAI1_TX1		\
-		(_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+		(_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
 #define  MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26		\
 		(_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4		\