ENGR00152845-1 MSL plat-mxc: ipuv3 display support in imx6q

1. work for multiple ipu instance

2. add mxc_dispdrv support
 A display device driver could call mxc_dispdrv_register(drv) in its
 dev_probe() function.
 - Move all dev_probe() things into mxc_dispdrv_driver->init(), init()
   function should init and feedback setting;
 - Move all dev_remove() things into mxc_dispdrv_driver->deinit();
 - Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
 - Move all dev_resume() things into fb_notifier for RESUME, if there is;

 ipuv3 fb driver would call mxc_dispdrv_init(drv_name, setting) before a
 fb need be added, with fbi param passing by setting, after mxc_dispdrv_init()
 return, FB driver should get the basic setting about fbi info and ipuv3-hw
 (ipu_id and disp_id).

 there are many display interfaces on imx5x or imx6x platform, all of them
 are connected with ipuv3-DI, mxc_dispdrv can register display device as:

	 "lcd"	--	display extend port for lcdif
	 "ldb"	--	lvds bridge on chip (imx5x or imx6x)
	 "tve"	--	tve for tveout on chip (imx5x)
	 "vga"	--	vga through tve on chip (imx5x)
	 "hdmi"	--	hdmi on platform with ddc support
			(sii902x on imx53 - not enable yet)
			hdmi on chip with ddc support
			(imx6x - not enable yet)
	 "dvi"	--	dvi port with ddc support (not enable yet)

 take tvout as example, a dispdrv structure and register flow could like below:

	 static struct mxc_dispdrv_driver tve_drv = {
	       .name   = "tve",
	       .init   = tvout_init,
	       .deinit = tvout_deinit,
	 };

 	mxc_dispdrv_register(&tve_drv);

 in ipuv3 fb driver could init tve driver like below:

	 setting.if_fmt = interface_pix_fmt;
	 setting.dft_mode_str = mode_str;
	 setting.default_bpp = default_bpp;
	 setting.fbi = fbi;
	 mxc_dispdrv_init("tve", &setting);

 based on mxc_dispdrv framework, display cmdline option will become
 as below (take mx53 loco board as example -- fb0 for wvga lcd, fb1 for
 XGA vga):

 	video=mxcfb0:dev=lcd,800x480M@55,if=RGB565
	video=mxcfb1:dev=vga,VGA-XGA,if=GBR24

 "mxcfb0" means setting for fb0 device, ipuv3 fb driver will request setting
 from registered dispdrv, these setting include what's the ipu and what's the
 DI number this dev used. Normally, if one IPU is first used, ipuv3 fb driver
 will create one overlay fb right after current fb driver create.
 Take above cmdline as an example,
 /dev/fb0 will be first fb device on 800x480 lcd.
 /dev/fb1 will be overlay fb device on 800x480 lcd.
 /dev/fb2 will be second fb device on VGA-XGA vga.

 "dev=" means which display device(lcd,ldb,vga etc) you want choose for this fb.
 "800x480M@55 or VGA-XGA" means the mode_str of video mode you want.
 "if=" means the display device hw interface format.

 such setting could be passed by platform data as a default value, cmdline
 option will replace these values if there are.

3. modify ldb/tve driver and add mxc_lcdif driver.
 For ldb driver, there are below modes could be set by cmdline options:

 "ldb=spl0/1"	--	split mode on DI0/1
 "ldb=dul0/1"	--	dual mode on DI0/1
 "ldb=sin0/1"	--	single mode on DI0/1
 "ldb=sep"	--	separate mode

 there are two LVDS channels(LVDS0 and LVDS1) which can transfer video datas,
 there two channels can be used as split/dual/single/separate mode.

 split mode means display data from DI0 or DI1 will send to both channels
 LVDS0+LVDS1.
 dual mode means display data from DI0 or DI1 will be duplicated on LVDS0 and
 LVDS1, it said, LVDS0 and LVDS1 has the same content.
 single mode means only work for DI0->LVDS0 or DI1->LVDS1.
 separate mode means you can make DI0->LVDS0 and DI1->LVDS1 work at the same
 time.

Signed-off-by: Jason Chen <jason.chen@freescale.com>

1 files changed, 7 insertions, 2 deletions

diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 835708c445bd..9e44eaa4824c 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -65,9 +65,14 @@
 #else
 #define MX3_IPU_IRQS 0
 #endif
-/* REVISIT: Add IPU irqs on IMX51 */
 
-#define NR_IRQS			(MXC_IPU_IRQ_START + MX3_IPU_IRQS)
+#ifdef CONFIG_ARCH_MX5
+#define MX5_IPU_IRQS (32*15)
+#else
+#define MX5_IPU_IRQS 0
+#endif
+
+#define NR_IRQS	(MXC_IPU_IRQ_START + MX3_IPU_IRQS + MX5_IPU_IRQS)
 
 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);