diff options
| author | Alison Wang <b18965@freescale.com> | 2012-12-11 15:32:19 +0800 |
|---|---|---|
| committer | Ed Nash <enash@enash-desktop.(none)> | 2012-12-12 14:46:30 -0500 |
| commit | efe491be15ead3bbcf7e715337fdee7dfa41f699 (patch) | |
| tree | 994f0d44a53f97a8cb35bece0fc0c25536e8fb80 /arch/arm/plat-mxc/include/mach/mvf.h | |
| parent | 7974a95ddfa0ad24e6d3684f350b7bfd84feb816 (diff) | |
ENGR00216076-1: PM: Add Power Management driver for Vybrid
System could run into STOP and LPRun modes. When system was working in STOP mode,
pressing SW1 button or inserting or removing SD card could wake up it.
Signed-off-by: Alison Wang <b18965@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mvf.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mvf.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index 9ef4de35d4c0..1e3f74f98857 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -53,8 +53,7 @@ * IRAM */ #define MVF_IRAM_BASE_ADDR 0x3F000000 /* internal ram */ -#define MVF_IRAM_PARTITIONS 2 -#define MVF_IRAM_SIZE (MVF_IRAM_PARTITIONS * SZ_256K) /* 512KB */ +#define MVF_IRAM_SIZE (SZ_256K) /* 256KB */ #ifdef CONFIG_MXC_VPU_IRAM @@ -169,12 +168,12 @@ #define MVF_EWM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00065000) #define MVF_I2C0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00066000) #define MVF_I2C1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00067000) -#define MVF_WKUP_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006A000) +#define MVF_WKPU_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006A000) #define MVF_CCM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006B000) -#define MVF_GPC_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006C000) -#define MVF_VREG_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006D000) -#define MVF_SRC_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006E000) +#define MVF_GPC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006C000) +#define MVF_VREG_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006D000) +#define MVF_SRC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006E000) #define MVF_CMU_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006F000) #define L2_BASE_ADDR MVF_L2C_BASE_ADDR @@ -283,6 +282,12 @@ #define MVF_PGC_GPU_PGCR (MVF_PGC_GPU_BASE + 0x0) #define MVF_PGC_GPU_PGSR (MVF_PGC_GPU_BASE + 0xC) +/* Voltage Regulators */ +#define MVF_VREG_BASE (MVF_IO_ADDRESS(MVF_VREG_BASE_ADDR)) + +/* WKPU */ +#define MVF_WKPU_BASE (MVF_IO_ADDRESS(MVF_WKPU_BASE_ADDR)) + /* * defines for SPBA modules */ |