diff options
| author | Peter Chen <peter.chen@freescale.com> | 2011-11-03 13:57:25 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-01-09 21:04:30 +0800 |
| commit | 1792e44faa0b51d2ffb6d4cd094f3b98f491ce6b (patch) | |
| tree | 2994b0e0c14cb570776e36581b441701dac0065d /arch/arm/plat-mxc/include/mach/mx6.h | |
| parent | 0b18f7add1ca5a4b04f9bc2b1f401f8978ed8694 (diff) | |
ENGR00161314-1 mx6q usb-host: add hsic support
MSL part
Add HSIC support for Host2 and Host3, for HSIC mode, there
is not usb phy needed, the usb device is always at the board
- Validation hardware: iMX6Q Validation Port Card and Re-worked
Rev X3 board, for hardware rework detail, contact Ken Sun (b03826)
- Validation device: HSIC interface SMSC HUB(USB4640) and Host 3.
Host 2 is coding finishes, but not verified due to hardware limitation.
- Pin Conflict with Ethernet, order to use HSIC, the user need
disable ethernet function at both u-boot and linux kernel.
For u-boot: please undefine CONFIG_MXC_FEC at your board config file
For kernel: please define CONFIG_USB_EHCI_ARC_HSIC, the entry is:
Device Drivers---> USB support---> Support HSIC Host controller
for Freescale SoC
- Suspend/resume and wakeup are not supported due to IC issues,
these IC issues will be fixed at TO1.1 for i.mx6, software will
add these support after receiving TO1.1 chip.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx6.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx6.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index 6658138ae14c..81c90e75b66d 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -200,6 +200,8 @@ #define MX6Q_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define MX6Q_USB_OTG_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) #define MX6Q_USB_HS1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4200) +#define MX6Q_USB_HS2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4400) +#define MX6Q_USB_HS3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4600) #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x8000) #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC000) @@ -325,6 +327,12 @@ #define MX6Q_INT_USB_OTG 75 #define MX6Q_INT_USB_PHY0 76 #define MX6Q_INT_USB_PHY1 77 +/* + * MX6Q_INT_USB_PHY2, MX6Q_INT_USB_PHY3 are dummy interrupts + * In order to compile pass for platform device's definition + */ +#define MX6Q_INT_USB_PHY2 73 +#define MX6Q_INT_USB_PHY3 74 #define MX6Q_INT_SSI1 78 #define MX6Q_INT_SSI2 79 #define MX6Q_INT_SSI3 80 |