diff options
| author | Alison Wang <b18965@freescale.com> | 2012-09-12 15:10:48 +0800 |
|---|---|---|
| committer | Andy Voltz <andy.voltz@timesys.com> | 2012-10-17 14:37:22 -0400 |
| commit | 684e7945da98ee5c820542b578278bd4632b6888 (patch) | |
| tree | 59ce535fc8bc02373397cd17cf05fb24d15efa83 /arch/arm/plat-mxc/include | |
| parent | 163da8b897550dad394cd1483c6bca9aa730c8e1 (diff) | |
ENGR00180953-1: dspi: update platform support for dspi driver
Update platform support for dspi driver after debugging on board.
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Alison Wang <b18965@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc/include')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/iomux-mvf.h | 2 | ||||
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/spi-mvf.h | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h index 775b0eb5d484..3c46ad41e8eb 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h @@ -118,7 +118,7 @@ typedef enum iomux_config { MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_ENABLE) #define MVF600_PAD44_PTB22__DSPI0_SCK \ IOMUX_PAD(0x00B0, 0x00B0, 1, 0x0000, 0, \ - MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) + MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_ENABLE) /*FEC0*/ #define MVF600_PAD0_PTA6__RMII_CLKIN \ diff --git a/arch/arm/plat-mxc/include/mach/spi-mvf.h b/arch/arm/plat-mxc/include/mach/spi-mvf.h index 4db9f9502661..4a05f3b349af 100644 --- a/arch/arm/plat-mxc/include/mach/spi-mvf.h +++ b/arch/arm/plat-mxc/include/mach/spi-mvf.h @@ -71,7 +71,7 @@ struct spi_mvf_master { #define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28) #define SPI_PUSHR_EOQ (1 << 27) #define SPI_PUSHR_CTCNT (1 << 26) -#define SPI_PUSHR_PCS(x) (((x) & 0x0000003f) << 16) +#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) #define SPI_PUSHR_SLAVE 0x34 @@ -91,7 +91,7 @@ struct spi_mvf_master { #define SPI_FRAME_BITS SPI_CTAR_FMSZ(0xf) #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) -#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0xf) +#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) #define SPI_CS_INIT 0x01 #define SPI_CS_ASSERT 0x02 |