ENGR00154211 [MX6]Add workaround for wdog errata

Errata number:TKT039676

WDOG sw reset is generated by writing to its
control register. WDOG's reset is activated by
ipg_clk_s, and is de-activated (later) by a
synchronized CKIL (32KHz clock). On the other
hand SRC samples the WDOG reset with an
unsynchronized CKIL clock. If the write to WDOG
control register happens between the edges of
unsynchronized and synchronized CKIL clocks SRC
will miss the wdog reset pulse.

Workaround: write wdog control register twice.

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 383013c7c76d..cadf3bb23275 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -43,6 +43,10 @@ void arch_reset(char mode, const char *cmd)
 	/* wait for reset to assert... */
 	wcr_enable = (1 << 2);
 	__raw_writew(wcr_enable, wdog_base);
+	/* errata TKT039676, SRS bit may be missed when
+	SRC sample it, need to write the wdog controller
+	twice to avoid it */
+	__raw_writew(wcr_enable, wdog_base);
 
 	/* wait for reset to assert... */
 	mdelay(500);