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authorRob Herring <r.herring@freescale.com>2010-02-01 17:29:57 -0200
committerAlejandro Gonzalez <alex.gonzalez@digi.com>2010-05-24 12:16:00 +0200
commitd853de63d39096d43dc2fdbe494b8cd9cfe9a251 (patch)
tree2696d8d31820fb740b8935d559b1bbebc3ab5f73 /arch/arm/plat-mxc
parenta68365507942861ae2ce9e4dc4e225977a96f15f (diff)
ENGR00120394-2 imx: make tzic use dynamic base address
Different chips have TZIC interrupt controller at different addresses, so make the mapping dynamic. Signed-off-by: Rob Herring <r.herring@freescale.com> Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S5
-rw-r--r--arch/arm/plat-mxc/tzic.c10
3 files changed, 15 insertions, 5 deletions
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index b66644df843c..4e84f404347f 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -23,6 +23,9 @@ extern void mx35_map_io(void);
extern void mx37_map_io(void);
extern void mx51_map_io(void);
extern void mxc_init_irq(void);
+extern void mx51_init_irq(void);
+extern void mx37_init_irq(void);
+extern void mxc_tzic_init_irq(unsigned long);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
extern int mx1_clocks_init(unsigned long fref);
extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 92f553baf447..b2f41ef09f3c 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -11,6 +11,8 @@
#include <mach/hardware.h>
+.extern tzic_base
+
#define AVIC_NIMASK 0x04
@ this macro disables fast irq (not implemented)
@@ -19,7 +21,8 @@
.macro get_irqnr_preamble, base, tmp
#ifdef CONFIG_MXC_TZIC
- ldr \base, =TZIC_IO_ADDRESS(TZIC_BASE_ADDR)
+ ldr \tmp, =tzic_base
+ ldr \base, [\tmp]
#else
ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
#ifdef CONFIG_MXC_IRQ_PRIOR
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 630d9f789f95..bcca6ac465a2 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -26,7 +26,9 @@
* TZIC Registers *
*****************************************
*/
-#define TZIC_BASE IO_ADDRESS(TZIC_BASE_ADDR)
+void __iomem *tzic_base;
+
+#define TZIC_BASE (tzic_base)
#define TZIC_INTCNTL (TZIC_BASE + 0x0000) /* control register */
#define TZIC_INTTYPE (TZIC_BASE + 0x0004) /* Controller type register */
#define TZIC_IMPID (TZIC_BASE + 0x0008) /* Distributor Implementer Identification Register */
@@ -117,10 +119,12 @@ static struct irq_chip mxc_tzic_chip = {
* interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source.
*/
-void __init mxc_init_irq(void)
+void __init mxc_tzic_init_irq(unsigned long base)
{
int i;
+ tzic_base = ioremap(base, SZ_4K);
+
/* put the TZIC into the reset value with
* all interrupts disabled
*/