diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-30 14:45:10 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-31 00:07:58 -0500 |
| commit | 5fd60addbbc2ca8083b15378fa460e41f5d94326 (patch) | |
| tree | 1078cf35cf940b4407ce0263a457b6bd71febd3c /arch/arm/plat-mxc | |
| parent | 4d64e8b36e4eb36ed5ad583f7c17b272ef464d7b (diff) | |
ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE support
Need to ensure that the ARM_CLK rate stays exactly the same
when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system
enters 24MHz state. Also need to ensure that PLL1 is enabled
before relocking the PLL to the correct rate.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/plat-mxc')
| -rwxr-xr-x | arch/arm/plat-mxc/include/mach/mxc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 3f58604f94dc..23159090ace8 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -249,6 +249,7 @@ extern unsigned int __mxc_cpu_type; struct cpu_op { u32 pll_reg; u32 pll_rate; + u32 pll_lpm_rate; u32 cpu_rate; u32 pdr0_reg; u32 pdf; |