diff options
| author | ming_qian <ming.qian@nxp.com> | 2018-12-27 09:30:58 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:35:48 +0800 |
| commit | 2243f7333b09e4289c4b6fe69ba49596c4b1f7b2 (patch) | |
| tree | f0ec147ca684cff8e1f90b192c75e1deb9aa1725 /arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts | |
| parent | 545031216a5a7b91f1a50e2f8e39f9672e76c8f8 (diff) | |
MLK-20659: VPU Encoder: refine code to reduce some hard code
Encoder driver use macro to define some register absolute address.
move the definition to dts, and use relative addresses to define
registers more clearly.
export these register definition through sysfs.
Signed-off-by: ming_qian <ming.qian@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts index b815faf38845..44e18f2125ff 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -294,18 +294,41 @@ vpu_encoder: vpu_encoder@2d000000 { compatible = "nxp,imx8qm-b0-vpuenc", "nxp,imx8qxp-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + boot-region = <&encoder_boot>; rpc-region = <&encoder_rpc>; - fw-buf-size = <0x200000 0x200000>; - rpc-buf-size = <0x80000 0x80000>; - print-buf-size = <0x80000 0x80000>; - reg = <0x0 0x2d000000 0x0 0x1000000>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ reg-names = "vpu_regs"; power-domains = <&pd_vpu_enc>; - reg-fw-base = <0x90000 0xa0000>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1080>; fps-max = <120>; status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; }; clk: clk { |