diff options
| author | Guoniu.Zhou <guoniu.zhou@nxp.com> | 2018-02-05 15:17:23 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:59 +0800 |
| commit | 23ae196e64b50edf9f6f4baab6c78202661abb0f (patch) | |
| tree | ee9cd0f37ff1d9e59422aff52604a985a15bc155 /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | |
| parent | 41965533d0b7db3573eed50c0c3c90288348a55c (diff) | |
MLK-17230-3: CI_PI: add device nodes for CI_PI SS
Add clock and power domain device nodes for CI_PI subsystem.
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 825392c25d2f3d430a877fc34e5268a4bd0324f0)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index 2d47413118a7..5fba80a1eaf3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -834,6 +834,35 @@ }; }; + pd_parallel_csi: PD_PARALLEL_CSI { + reg = <SC_R_PI_0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_parallel_csi_i2c0: PD_PARALLEL_CSI_I2C { + name = "parallel_csi_i2c"; + reg = <SC_R_PI_0_I2C_0>; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + + pd_parallel_csi_pwm0: PD_PARALLEL_CSI_PWM { + name = "parallel_csi_pwm"; + reg = <SC_R_PI_0_PWM_0>; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + + pd_parallel_csi_pll: PD_PARALLEL_CSI_PLL { + name = "parallel_csi_pll"; + reg = <SC_R_PI_0_PLL>; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + }; + pd_isi_ch1: PD_IMAGING_PDMA1 { reg = <SC_R_ISI_CH1>; #power-domain-cells = <0>; @@ -1561,7 +1590,7 @@ }; }; - camera { + cameradev: camera { compatible = "fsl,mxc-md", "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -1692,6 +1721,20 @@ status = "disabled"; }; + parallel_csi: pcsi@58261000 { + compatible = "fsl,mxc-parallel-csi"; + reg = <0x0 0x58261000 0x0 0x1000>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_PIXEL_CLK>, + <&clk IMX8QXP_PARALLEL_CSI_IPG_CLK>; + clock-names = "pixel", "ipg"; + assigned-clocks = <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, + <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>; + assigned-clock-parents = <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; + assigned-clock-rates = <0>, <160000000>; /* 160MHz */ + power-domains = <&pd_parallel_csi>; + status = "disabled"; + }; + jpegdec: jpegdec@58400000 { compatible = "fsl,imx8-jpgdec"; reg = <0x0 0x58400000 0x0 0x00040020 >; |