diff options
| author | Liu Ying <victor.liu@nxp.com> | 2017-06-20 17:39:22 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:29:47 +0800 |
| commit | 64a7eb034c1cca19f537103d9ad091acd6c75b41 (patch) | |
| tree | 6eab9cac3db089349406730a5235d7e3917201cf /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | |
| parent | 91ae6927e8f61a307421567543fc5c5e76b71d0d (diff) | |
MLK-15110-11 arm64: dtsi: fsl-imx8qxp: Add DPR0/1 irq resources for DPU
The Display Prefetch Resolve(DPR) engine is the prefetch engine of DPU.
This patch adds the DPR0/1's irq resources for DPU.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index f98e035fc3e2..1f7a6cc6491d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -967,7 +967,9 @@ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irq_common", "irq_stream0a", "irq_stream0b", /* to M4? */ @@ -975,7 +977,9 @@ "irq_stream1b", /* to M4? */ "irq_reserved0", "irq_reserved1", - "irq_blit"; + "irq_blit", + "irq_dpr0", + "irq_dpr1"; clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, <&clk IMX8QXP_DC0_PLL1_CLK>, <&clk IMX8QXP_DC0_DISP0_CLK>, |