diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2018-04-12 10:20:17 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:13 +0800 |
| commit | 64c2b8002fee44687a65c9e6572fde4f9e8424e1 (patch) | |
| tree | 31919a6478db1d8ca1b720f80abe2a35fdc90dfe /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | |
| parent | e579d0c204b4f26af786ee4b0d05594636215675 (diff) | |
MLK-18003 ARM64: dts: imx8qxp: change back usdhc clock parent to PLL0
8QXP B0 chip already fix the PLL0 unstable issue, so change back
the usdhc clock parent to PLL0.
To track the history, refer to commit 7834eee6dfa8 ("MLK-17188-2
ARM64: dts: imx8qxp: assign usdhc clock parent").
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index cc244d2a7e6f..da9b90ba828b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -2454,7 +2454,7 @@ <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; assigned-clock-rates = <0>, <400000000>; power-domains = <&pd_conn_sdch0>; fsl,tuning-start-tap = <20>; @@ -2472,7 +2472,7 @@ <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; assigned-clock-rates = <0>, <200000000>; power-domains = <&pd_conn_sdch1>; fsl,tuning-start-tap = <20>; @@ -2490,7 +2490,7 @@ <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; assigned-clock-rates = <0>, <200000000>; power-domains = <&pd_conn_sdch2>; status = "disabled"; |