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authorAlex Marginean <alexandru.marginean@nxp.com>2020-01-07 14:48:20 +0200
committerJason Liu <jason.hui.liu@nxp.com>2020-02-26 04:17:38 +0800
commit80bcf697df8a8ed597e8c222add00eb492125717 (patch)
treec569f967042579b0ddd55dc9850210bbb656b8bf /arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
parentaf9560bd3b3f345c36618d8639372a5dcbc899e8 (diff)
arm64: dts: fsl-ls1028a-qds: Add overlays for various serdes protocols
Adds overlays for various serdes protocols on LS1028A QDS board using different PHY cards. These should be applied at boot, based on serdes configuration. If no overlay is applied, only the RGMII interface on the QDS is available in Linux. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> (cherry picked from commit 779c69e4ae9d1535e958cda7309f030293e3c45c)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts93
1 files changed, 93 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
new file mode 100644
index 000000000000..88c415644b29
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85bb
+ *
+ * Copyright 2019 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@1c {
+ /* 1st port on VSC8234 */
+ reg = <0x1c>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "sgmii";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+};