diff options
| author | Ran Wang <ran.wang_1@nxp.com> | 2019-12-25 14:00:27 +0800 |
|---|---|---|
| committer | Ran Wang <ran.wang_1@nxp.com> | 2019-12-25 15:11:02 +0800 |
| commit | bcae63bb27e513e90d22477029017e9fe0971bff (patch) | |
| tree | b1f4c6feca6e9c437b200d646bc5731807056bf8 /arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | |
| parent | fc01006503af66006c09e3fcf63dce852a0aab57 (diff) | |
arm64: dts: layerscape: apply dma-coherent for dwc3 nodes
Since dwc3 cache type has been set to cacheable, apply dma-coherent to
all dwc3 nodes accordingly.
Note: For LS1043A and LS1046A, since QE-HDLC still doesn't support
dma-coherent, we cannot directly revert cd1a4f3c (sdk: dts: ls104x move
dma-coherent from soc to its child nodes) to recover dma-coherent for
soc.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 7e5e4a2fbd7e..3218d69df3a6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -874,6 +874,7 @@ snps,dis_rxdet_inp3_quirk; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; snps,host-vbus-glitches; + dma-coherent; status = "disabled"; }; |