diff options
| author | Abel Vesa <abel.vesa@nxp.com> | 2021-06-08 17:47:52 +0300 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:57 +0800 |
| commit | 9b5dfdeb65f57d6fc64beba66ea0dfa158f164a3 (patch) | |
| tree | 4caa8d19f40febb2337e8db3b8d88f96b614848a /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | 230efd489cd8a626775a2e12844383d679be2625 (diff) | |
arm64: dts: freescale: Switch from clock-indices to bit-offsets
This is a temporary fix after rebasing the linux-nxp/dts/imx8
on top of next-20210514. The reason we're doing the switch is to
keep the dts working. The upstream version of the dts files already
use clock-indices. The NXP's tree needs to become ready to do so
too.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 7609a3ddfe25..15712124f96c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -208,8 +208,7 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; - clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, - <IMX_LPCG_CLK_5>; + bit-offset = <0 16 20>; clock-output-names = "sdhc0_lpcg_per_clk", "sdhc0_lpcg_ipg_clk", "sdhc0_lpcg_ahb_clk"; @@ -222,8 +221,7 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; - clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, - <IMX_LPCG_CLK_5>; + bit-offset = <0 16 20>; clock-output-names = "sdhc1_lpcg_per_clk", "sdhc1_lpcg_ipg_clk", "sdhc1_lpcg_ahb_clk"; @@ -236,8 +234,7 @@ conn_subsys: bus@5b000000 { #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; - clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, - <IMX_LPCG_CLK_5>; + bit-offset = <0 16 20>; clock-output-names = "sdhc2_lpcg_per_clk", "sdhc2_lpcg_ipg_clk", "sdhc2_lpcg_ahb_clk"; @@ -254,9 +251,7 @@ conn_subsys: bus@5b000000 { <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, <&conn_ipg_clk>, <&conn_ipg_clk>; - clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, - <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, - <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + bit-offset = <0 4 8 12 16 20>; clock-output-names = "enet0_lpcg_timer_clk", "enet0_lpcg_txc_sampling_clk", "enet0_lpcg_ahb_clk", @@ -276,9 +271,7 @@ conn_subsys: bus@5b000000 { <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, <&conn_ipg_clk>, <&conn_ipg_clk>; - clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, - <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, - <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; + bit-offset = <0 4 8 12 16 20>; clock-output-names = "enet1_lpcg_timer_clk", "enet1_lpcg_txc_sampling_clk", "enet1_lpcg_ahb_clk", |