diff options
| author | Peter Chen <peter.chen@nxp.com> | 2020-07-15 15:14:02 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:40 +0800 |
| commit | 613381a2387be1ce148d15bb376ea9717f1e0ea1 (patch) | |
| tree | 034ce9aa4834cc2ed7ae4766f7552548b7d463dd /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | a6761e17c999bd6ff84e4b3c03c22bbfd2abd395 (diff) | |
arm64: dts: imx8-ss-conn: apply changes for upstream Cadence USB3 driver
Change board dts as well to avoid bisect break, the main changes are
as belows:
- Add iommus phandle for core device
- delete core device node for xen dts
- Support mek board by adding Type-C support
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 49 |
1 files changed, 35 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 23f536cab8b1..997fe00d91f9 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -165,23 +165,22 @@ conn_subsys: bus@5b000000 { status = "disabled"; }; - usb3phynop1: usb3-phy { - compatible = "usb-nop-xceiv"; + usb3_phy: usb-phy@5b160000 { + compatible = "nxp,salvo-phy"; + reg = <0x5B160000 0x40000>; clocks = <&usb3_lpcg 4>; - clock-names = "main_clk"; + clock-names = "salvo_phy_clk"; power-domains = <&pd IMX_SC_R_USB_2_PHY>; + #phy-cells = <0>; status = "disabled"; - }; + }; - usbotg3: usb3@5b110000 { - compatible = "Cadence,usb3"; - reg = <0x5B110000 0x10000>, - <0x5B130000 0x10000>, - <0x5B140000 0x10000>, - <0x5B160000 0x40000>, - <0x5B120000 0x10000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + usbotg3: usb@5b110000 { + compatible = "fsl,imx8qm-usb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x5B110000 0x10000>; clocks = <&usb3_lpcg 1>, <&usb3_lpcg 0>, <&usb3_lpcg 5>, @@ -189,9 +188,31 @@ conn_subsys: bus@5b000000 { <&usb3_lpcg 3>; clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; power-domains = <&pd IMX_SC_R_USB_2>; - cdns3,usbphy = <&usb3phynop1>; status = "disabled"; + + usbotg3_cdns3: usb@5b120000 { + compatible = "cdns,usb3"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + reg = <0x5B130000 0x10000>, /* memory area for HOST registers */ + <0x5B140000 0x10000>, /* memory area for DEVICE registers */ + <0x5B120000 0x10000>; /* memory area for OTG/DRD registers */ + reg-names = "xhci", "dev", "otg"; + phys = <&usb3_phy>; + phy-names = "cdns3,usb3-phy"; + status = "disabled"; + }; }; /* LPCG clocks */ |