diff options
| author | Shenwei Wang <shenwei.wang@nxp.com> | 2022-07-08 10:16:59 -0500 |
|---|---|---|
| committer | Shenwei Wang <shenwei.wang@nxp.com> | 2022-07-08 11:50:30 -0500 |
| commit | 77ce497c9c91b167e94cdd98bb5ec49711240685 (patch) | |
| tree | 7e2014b3d7c4915caf71d55306e694c7023b5954 /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | 4d13ccbb0b288761614dec7940c5dea640dfebaf (diff) | |
LF-6447 arm64: dts: imx8: add default clock rate for usdhc
Add default clock rate for usdhc nodes.
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 582dbd5eaeea..04ab90081343 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -79,6 +79,8 @@ conn_subsys: bus@5b000000 { <&sdhc0_lpcg 0>, <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <400000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; @@ -92,6 +94,8 @@ conn_subsys: bus@5b000000 { <&sdhc1_lpcg 0>, <&sdhc1_lpcg 2>; clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; @@ -105,6 +109,8 @@ conn_subsys: bus@5b000000 { <&sdhc2_lpcg 0>, <&sdhc2_lpcg 2>; clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; |