diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-18 17:17:29 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:19 +0800 |
| commit | a180d06cdaf33586e668f0985ddb1a8d8161e011 (patch) | |
| tree | 9158b0d50f5bc3dc58d7479cc1311e8bf51eb38d /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | b0b0c2e764dd80ab888a4c937dfaaac662b16da0 (diff) | |
arm64: dts: imx8: conn: fully switched to new clk binding
fully switched to new clk binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index c0a5c02a8104..8b87c6edd342 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -42,7 +42,7 @@ conn_subsys: bus@5b000000 { interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; - clocks = <&conn_lpcg IMX_CONN_LPCG_USB2_AHB_CLK>; + clocks = <&usb2_lpcg 0>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -60,7 +60,7 @@ conn_subsys: bus@5b000000 { compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; reg = <0x5b100000 0x1000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_USB2_PHY_IPG_CLK>; + clocks = <&usb2_lpcg 1>; power-domains = <&pd IMX_SC_R_USB_0_PHY>; status = "disabled"; }; @@ -230,4 +230,15 @@ conn_subsys: bus@5b000000 { "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + bit-offset = <24 28>; + clock-output-names = "usboh3_ahb_clk", + "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; }; |