diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2021-06-09 16:22:19 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:57 +0800 |
| commit | af7d857dafeeb178f2e2db27ae13a59ce5fdd7f4 (patch) | |
| tree | a4d04d253f7d618fa37c9f41937c0479bfd8db33 /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | 5cffecd89745896f54ba8ad67afd098aa2812c5b (diff) | |
arm64: dts: imx: back to use bit-offset for LPCG
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 15712124f96c..582dbd5eaeea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -75,9 +75,9 @@ conn_subsys: bus@5b000000 { usdhc1: mmc@5b010000 { interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; - clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, - <&sdhc0_lpcg IMX_LPCG_CLK_5>, - <&sdhc0_lpcg IMX_LPCG_CLK_0>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_0>; fsl,tuning-start-tap = <20>; @@ -88,9 +88,9 @@ conn_subsys: bus@5b000000 { usdhc2: mmc@5b020000 { interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b020000 0x10000>; - clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, - <&sdhc1_lpcg IMX_LPCG_CLK_5>, - <&sdhc1_lpcg IMX_LPCG_CLK_0>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -101,9 +101,9 @@ conn_subsys: bus@5b000000 { usdhc3: mmc@5b030000 { interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b030000 0x10000>; - clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, - <&sdhc2_lpcg IMX_LPCG_CLK_5>, - <&sdhc2_lpcg IMX_LPCG_CLK_0>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_2>; fsl,tuning-start-tap = <20>; @@ -117,11 +117,12 @@ conn_subsys: bus@5b000000 { <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, - <&enet0_lpcg IMX_LPCG_CLK_2>, - <&enet0_lpcg IMX_LPCG_CLK_3>, - <&enet0_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + clocks = <&enet0_lpcg 4>, + <&enet0_lpcg 2>, + <&enet0_lpcg 3>, + <&enet0_lpcg 0>, + <&enet0_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; @@ -137,11 +138,12 @@ conn_subsys: bus@5b000000 { <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, - <&enet1_lpcg IMX_LPCG_CLK_2>, - <&enet1_lpcg IMX_LPCG_CLK_3>, - <&enet1_lpcg IMX_LPCG_CLK_0>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + clocks = <&enet1_lpcg 4>, + <&enet1_lpcg 2>, + <&enet1_lpcg 3>, + <&enet1_lpcg 0>, + <&enet1_lpcg 1>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; assigned-clock-rates = <250000000>, <125000000>; |