diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2019-11-08 10:22:31 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:40 +0800 |
| commit | c1e14884a3bdcc64cdf077dad38f5ed4123d1de3 (patch) | |
| tree | c2f46100778beec349f0a1ca8a084e8938711213 /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | 7f0da9ae9954e2ff8df15ac910a47dda8aa5f741 (diff) | |
MLK-22930 ARM64: dts: change the source clock rate of usdhc1 for imx8qxp/imx8qm
On imx8qxp and imx8qm mek board, usdhc1 is for eMMC usage, and will work at
HS400 mode, this HS400 mode will work at 200MHz, and will default divide 2 from
source clock(IMX_SC_R_SDHC_0), which mean we need to config the source clock
to 400MHz at least.
Before this patch, HS400 mode only work at 100MHz, and will meet some timeout issue
when do system suspend/resume, due to our HS400 related timing setting is based on
the 200MHz. Also, HS400 work at 100MHz will impact the performance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index a8083e0531ee..f23d45f1ee87 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -73,7 +73,7 @@ conn_subsys: bus@5b000000 { <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <400000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; |