diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-15 16:06:44 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:51 +0800 |
| commit | df244316e4feed2a1e07c5e5c3e17ff990ec9b71 (patch) | |
| tree | 840e6d99d8c98a0eb22e82563fce875559976c1c /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | |
| parent | 5b6c64df1e7f90a17ad6785c4c43b2bd258ffa46 (diff) | |
arm64: dts: imx8: switch to two cell scu clock binding
switch to two cell scu clock binding
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 0e0b0ef9f805..1339139a4555 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -72,7 +72,7 @@ conn_subsys: bus@5b000000 { <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; fsl,tuning-start-tap = <20>; @@ -88,7 +88,7 @@ conn_subsys: bus@5b000000 { <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -104,7 +104,7 @@ conn_subsys: bus@5b000000 { <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; fsl,tuning-start-tap = <20>; @@ -163,7 +163,7 @@ conn_subsys: bus@5b000000 { sdhc0_lpcg: clock-controller@5b200000 { reg = <0x5b200000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_SDHC0_CLK>, + clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; bit-offset = <0 16 20>; clock-output-names = "sdhc0_lpcg_per_clk", @@ -175,7 +175,7 @@ conn_subsys: bus@5b000000 { sdhc1_lpcg: clock-controller@5b210000 { reg = <0x5b210000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_SDHC1_CLK>, + clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; bit-offset = <0 16 20>; clock-output-names = "sdhc1_lpcg_per_clk", @@ -187,7 +187,7 @@ conn_subsys: bus@5b000000 { sdhc2_lpcg: clock-controller@5b220000 { reg = <0x5b220000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_SDHC2_CLK>, + clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; bit-offset = <0 16 20>; clock-output-names = "sdhc2_lpcg_per_clk", @@ -199,8 +199,8 @@ conn_subsys: bus@5b000000 { enet0_lpcg: clock-controller@5b230000 { reg = <0x5b230000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, - <&clk IMX_CONN_ENET0_ROOT_CLK>, + clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; bit-offset = <0 4 8 16 20>; clock-output-names = "enet0_ipg_root_clk", @@ -214,8 +214,8 @@ conn_subsys: bus@5b000000 { enet1_lpcg: clock-controller@5b240000 { reg = <0x5b240000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, - <&clk IMX_CONN_ENET1_ROOT_CLK>, + clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; bit-offset = <0 4 8 16 20>; clock-output-names = "enet1_ipg_root_clk", |