diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2019-07-26 14:28:18 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:18 +0800 |
| commit | 14fe1de8bc38f94fc7063ca8a0be11ddde015307 (patch) | |
| tree | 541e8aa062af05fb64ef82bf558214e4d237dcb7 /arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | |
| parent | bc224ea99032e9153fc1aaea04dcabf1993ec6f6 (diff) | |
arch: arm64: imx8qxp: drop multi-pd for CAN device
From HW point of view, CAN1/2 do not depend on CAN0 PD, it just uses
CAN0 clock which could be handled by clock driver itself. Now clock
runtime pm has support it, so drop multi-pd for CAN1/2.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index c94b3878fc20..a0e2389394d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -293,17 +293,16 @@ dma_subsys: bus@5a000000 { reg = <0x5a8e0000 0x10000>; interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - /* CAN0 clock and PD is shared among all CAN instances */ + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ clocks = <&can0_lpcg 1>, <&can0_lpcg 0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; - /* CAN1 shares CAN0's clock, to enable CAN0's clock it has - * to be powered on, so CAN1 depends on CAN0's power domain. - */ - power-domains = <&pd IMX_SC_R_CAN_1>, <&pd IMX_SC_R_CAN_0>; - power-domain-names = "can_pd", "can_aux_pd"; + power-domains = <&pd IMX_SC_R_CAN_1>; /* SLSlice[4] */ fsl,clk-source = <0>; status = "disabled"; @@ -314,17 +313,16 @@ dma_subsys: bus@5a000000 { reg = <0x5a8f0000 0x10000>; interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; - /* CAN0 clock and PD is shared among all CAN instances */ + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ clocks = <&can0_lpcg 1>, <&can0_lpcg 0>; clock-names = "ipg", "per"; assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <40000000>; - /* CAN2 shares CAN0's clock, to enable CAN0's clock it has - * to be powered on, so CAN2 depends on CAN0's power domain. - */ - power-domains = <&pd IMX_SC_R_CAN_2>, <&pd IMX_SC_R_CAN_0>; - power-domain-names = "can_pd", "can_aux_pd"; + power-domains = <&pd IMX_SC_R_CAN_2>; /* SLSlice[4] */ fsl,clk-source = <0>; status = "disabled"; |