diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2019-11-12 14:59:59 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:44 +0800 |
| commit | 2f6b19528e7a206d99b131b7fbfb0f0b9cbac27d (patch) | |
| tree | a66d3978078ce40e0c690204b63ef843c81114d1 /arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | |
| parent | eb0faf129676e72137a44b92bb17d45e1bf31ee1 (diff) | |
MLK-22921-4 ARM64: dts: imx8qxp/qm: add lpspi dts files
Add lpspi mater and slave dts files for imx8qxp/qm platforms.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6feb7d1129e6..dab01d97a3ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -22,6 +22,8 @@ dma_subsys: bus@5a000000 { lpspi0: spi@5a000000 { compatible = "fsl,imx7ulp-spi"; reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&spi0_lpcg 0>, @@ -36,6 +38,8 @@ dma_subsys: bus@5a000000 { lpspi2: spi@5a020000 { compatible = "fsl,imx7ulp-spi"; reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clocks = <&spi2_lpcg 0>, @@ -47,6 +51,22 @@ dma_subsys: bus@5a000000 { status = "disabled"; }; + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + status = "disabled"; + }; + lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; @@ -197,6 +217,18 @@ dma_subsys: bus@5a000000 { power-domains = <&pd IMX_SC_R_SPI_2>; }; + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + uart0_lpcg: clock-controller@5a460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; |