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authorRobert Chiras <robert.chiras@nxp.com>2020-05-22 15:09:39 +0300
committerRobert Chiras <robert.chiras@nxp.com>2020-08-21 15:32:12 +0300
commit4ee1ddfdcefce34df9290c9f1f531bb93a89608e (patch)
tree21a5df34a1da320413d5d8933eb592b2711c4a63 /arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
parent6024c8cbc3f75b997cd3d537269bc2c0b11c2408 (diff)
MLK-24334-9: arch: arm64: dts: imx8dxl: unify adma_lcdif
Currently, the adma_lcdif and it's related nodes are duplicated in 8qxp and 8dxl dts files. Since it's the same subsystem, move these nodes into generic files, so that both 8qxp and 8dxl dts files can use them. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 5e2cc2787716..e33c2080ce3c 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -583,4 +583,29 @@ dma_subsys: bus@5a000000 {
compatible = "fsl,i2c-rpbus";
status = "disabled";
};
+
+ adma_pwm: pwm@5a190000 {
+ compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+ reg = <0x5a190000 0x1000>;
+ clocks = <&adma_pwm_lpcg 0>, <&adma_pwm_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
+ status = "disabled";
+ };
+
+ adma_pwm_lpcg: clock-controller@5a590000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a590000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ bit-offset = <0 16>;
+ clock-output-names = "adma_pwm_lpcg_clk",
+ "adma_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>;
+ status = "disabled";
+ };
};