diff options
author | Robert Chiras <robert.chiras@nxp.com> | 2020-05-22 15:09:39 +0300 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:52 +0800 |
commit | cb49e510709d95579a044f0da4d79edb0022efb7 (patch) | |
tree | 0c72f57225366de1621dfe55829bb464436850a4 /arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi | |
parent | 4bad9c8af9d0ee7b62c88db117fcacd2c2ec796e (diff) |
MLK-24334-9: arch: arm64: dts: imx8dxl: unify adma_lcdif
Currently, the adma_lcdif and it's related nodes are duplicated in 8qxp
and 8dxl dts files. Since it's the same subsystem, move these nodes into
generic files, so that both 8qxp and 8dxl dts files can use them.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi new file mode 100644 index 000000000000..4bf058106fec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lcdif.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +lcdif_subsys: bus@5a180000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a180000 0x0 0x5a180000 0x500000>; + + ipg_dma_clk: clock-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "ipg_dma_clk"; + }; + + lcd_clk_lpcg: clock-controller@5a580000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a580000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&ipg_dma_clk>; + bit-offset = <0 16>; + clock-output-names = "lcd_clk_lpcg", "lcd_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0>; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x5a180000 0x10000>; + clocks = <&lcd_clk_lpcg 0>, + <&lcd_clk_lpcg 1>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>; + assigned-clock-parents = <&clk IMX_SC_R_ELCDIF_PLL IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + assigned-clock-rates = <0>, <24000000>, <804000000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + }; +}; |