diff options
| author | Adam Ford <aford173@gmail.com> | 2021-01-10 05:38:26 -0600 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-01-18 08:16:31 +0800 |
| commit | e8d08d80f4508e0601ea2beb0848b5a60d6a2c31 (patch) | |
| tree | e07126427da325642e2f2b3acfebfa5e97e68ab8 /arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | |
| parent | 8900d0d59b63766c4ed10462eb921c4bd595e4c7 (diff) | |
arm64: dts: imx8mm-beacon: add more pinctrl states for usdhc1
The WiFi chip is capable of communication at SDR104 speeds.
Enable 100Mhz and 200MHz pinmux to support this.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index d897913537ca..988f8ab679ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -256,8 +256,10 @@ &usdhc1 { #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <4>; non-removable; cap-power-off-card; |