diff options
| author | Guoniu.zhou <guoniu.zhou@nxp.com> | 2020-09-18 16:17:34 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:50:35 +0800 |
| commit | 57d30dd4436f478acbc4a9989fcc1e74fb87853c (patch) | |
| tree | d118d9cf3fedf071fe7467ac4476731379ad5389 /arch/arm64/boot/dts/freescale/imx8mp-evk.dts | |
| parent | 55febedb8c0fc3ef8bd523850dd998bbe4a0b6dc (diff) | |
MLK-24494-5: arm64: dts: imx8mp: add dts for ov2775 and ov5640 support
Add dts for OV2775 + OV5640 for iMX865-EVK board. OV2775 connect to
CSI port 0 and OV5640 connect to CSI port 1, as bellow:
OV2775 => CSI1
OV5640 => CSI2
Board need to rework to support this feature. More info, please
refer to rework guide provided by NXP
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 818a0d727062..9e7fb2b48006 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -390,7 +390,7 @@ compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; @@ -482,7 +482,7 @@ compatible = "ovti,ov5640"; reg = <0x3c>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; @@ -1082,7 +1082,12 @@ pinctrl_csi0_rst: csi0_rst_grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 - MX8MP_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x59 >; }; }; |